搜索资源列表
-
0下载：
用VHDL实现的ZigBee模块控制算法以及AES加密算法，用于Xilinx的FPGA!-With the realization of VHDL ZigBee module control algorithm and AES encryption algorithms for Xilinx FPGA!
-
-
0下载：
aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
-
-
1下载：
用XILINX公司提供的NetFPGA板卡并结合软件Xilinx10.1进行系统设计，采用硬件描述语言Verilog实现了 AES-256加密算法。-Provided by XILINX board combined with software Xilinx10.1 NetFPGA system design, using Verilog hardware descr iption language implementation of the AES-256 encryption algorit
-
-
0下载：
vhdl implementation of the AES encryption algorithm
-
-
0下载：
AES Encryption Algorithm....
This Module gives the basic overview to indicate the flow of AES Algorithim at different stages by associating various Packages to the module-AES Encryption Algorithm....
This Module gives the basic overview to
-
-
0下载：
implementation of AES encryption algorithm in vhdl/verilog
-
-
0下载：
AES加密算法的Verilog语言实现，通过编译-AES encryption algorithm in Verilog Implementation
-
-
0下载：
AES algorithm encryption and display on FPGA spartran 2e
-
-
0下载：
一种实用的基于FPGA的加密算法的设计，有AES和DES-A practical FPGA-based design of encryption algorithm, AES and DES have
-
-
1下载：
Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.
-
-
0下载：
本文介绍了AES 数据加密结构, 以及相关的有限域的知识及简单运算, 提出了一种用FPGA 高速实现AES 算法的方案, 该方
案设计的加密模块支持AES 标准的三种密钥长度: 128,192,256, 支持ECB, CBC, CTR 三种工作模式, 即支持feedback 和non- feedback
两种模式, 最后给出了本设计的性能指标-This article describes the AES data encryption structure, as well as the
-
-
0下载：
aes加密算法的Verilog语言实现（顶层代码，已编译，无错误）-aes encryption algorithm of Verilog language (top-level code, compile, no error)
-
-
0下载：
对AES算法加密解密的Verilog源代码，可以实现其128位和256位明文密文之间的转换。-AES algorithm for encryption and decryption of Verilog source code, can achieve the conversion of its 128 and 256 between the plaintext ciphertext.
-
-
0下载：
AES算法加解密过程的Verilog代码，包括测试文件，通过FPGA验证。-AES algorithm encryption and decryption process Verilog code, including test files through the FPGA verification.
-
-
0下载：
AES加密和解密算法的硬件语言描述，很值得大家来学习！-AES hardware encryption and decryption algorithm descr iption language, it is worth learning!
-
-
0下载：
AES算法部分模块行位移列变换以及主题程序加密解密-AES algorithm transforms part of the module rows and columns relating to the displacement of encryption and decryption program
-
-
2下载：
AES加密算法verilog代码实现，基于APB总线接口数字IP，包含详细的testbench-AES encryption algorithm verilog code, based on the APB bus interface digital IP, contains a detailed testbench
-
-
1下载：
AES加密算法中的列混合模块的FPGA实现源代码，采用Verillog语言，在软件Quartus II上综合-AES encryption algorithm in the FPGA column hybrid module implementation source code, using language Verillog integrated in the Quartus II software
-
-
1下载：
AES 加密算法 基于流水线设计 成熟IP core-AES encryption algorithm based on pipeline design mature IP core
-
-
0下载：
We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely
-
