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FFT-IP.介绍了基于FPGA的FFT实现方法
- 介绍了基于FPGA的FFT实现方法，并给出了实例程序，程序通过验证，可以直接使用,FPGA based on the realization of the FFT method, and gives examples of procedures, procedures for the adoption of authentication, can be directly used
fir_hdl.rar
- 一个 FIR 滤波器的 verilog 实现， 与 matlab 产生的 reference code 相互验证。,Verilog a FIR filter to achieve, with the reference code generated by matlab mutual authentication.
i2c_slave
- i2c slave 分享給大家驗證有點issue-i2c slave to everyone to share a bit authentication issue
traffic_controller
- 实现交通灯控制器的vhdl编程，并且经过下载验证-Implementation of traffic light controller VHDL programming, and has gone through a download authentication
butterfly
- 蝶形运算的VHDL代码，可以实现，没验证-VHDL code butterfly operations can be achieved, no authentication
20081129464173846
- 介绍Verilog HDL, 内容包括： – Verilog应用 – Verilog语言的构成元素 – 结构级描述及仿真 – 行为级描述及仿真 – 延时的特点及说明 – 介绍Verilog testbench • 激励和控制和描述 • 结果的产生及验证 – 任务task及函数function – 用户定义的基本单元(primitive) – 可综合的Verilog描述风格-Introduced the Verilog HDL, in
modesim
- 讲述使用modelsim进行验证，使用verilogHDL语言进行建模。其中还包括一个讲述怎样用verilog语言编写测试台的详细文档，对fpga cpld设计的后期验证有很大的帮助。-About the use modelsim for authentication, use verilogHDL language modeling. It also includes a focus on how to use verilog test bench written a detailed doc
serial
- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。 串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值 是0x104，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通 信同步. 程
FPGA_BASED_IMAGE_SECURITY
- FPGA based watermarked image security and authentication. I-FPGA based watermarked image security and authentication. IEEE
HDL-DE-KE-ZHONGHE-JIANJIE
- 分析：制定规范 设计：状态图，真值表，编写代码。 验证：证明电路的正确性。仿真和形式化验 证。 综合：高层次到低层次转换。生成网表 测试：发现废品。生成测试向量-Analysis: norm design: state diagram, truth table, write the code. Authentication: proof of the c
zjf10226jishuqi
- 10226计数器，vhdl语言设计，可在数码管上显示，可下载验证-10226 counter, vhdl language design can be displayed on the digital, downloadable authentication
verilog-encoder
- JPEG的編碼器 使用VERILOG以硬體實現 也使用MODEL模擬驗證-JPEG encoder using the VERILOG hardware implementation is also used to simulate authentication MODEL
demo_LCDdisplay
- DE2-70 LCDdisplay验证 FPGA-DE2-70 LCDdisplay authentication
yuv444_rgb888
- 实现了yuv444转rgb888，已经过verilog验证！-Implementation of YUV444 RGB888, has passed the Verilog authentication!
shift8
- 完成8位移位寄存器的VHDL设计、仿真、下载验证，要求有带进位循环右移、带进位循环左移、自循环右移和自循环左移功能。-Completed the 8-bit shift register VHDL design, simulation, download authentication, and require Rotate right, Rotate left, since the rotate right and left from the circulation function.
uart_Verilog
- 基于Verilog的RS232串口通信实验，可发送256位数据，并在Altera的EP4CE15F17C8芯片上验证成功。-Verilog-based RS232 serial communication experiment, 256-bit data can be sent on Altera' s EP4CE15F17C8 chip authentication is successful.
open_free_list_latest.tar
- Its a code for authentication to a memory related topic of the ddr series in the line to achive desired output
dram_latest.tar
- Its a code for authentication to a memory related topic of the ddr series in the line to achive desired output
MGC-07-H
- OPENice-i500仿真器验证实例，很实用，方便开发和验证-OPENice-i500 emulator authentication instance, it is useful to facilitate the development and validation
mips
- 基于MIPS架构实现的单周期处理器，包含多种基本操作，验证方法是把自己的学号写进连续内存。-MIPS-based architecture for single-cycle processor, includes a variety of basic operations, authentication method is to learn their numbers written contiguous memory.