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eqingdaqi
- VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现-VHDL electronic Responder realized. A number of documents, the main controls are using maps the bank. The remaining modules using VHDL
hssdrc_latest.tar.gz
- HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is li
polyphase
- The current portion of the collaboration has involved the feasibilty and implementation of a Polyphase Filter bank using various FPGAs and hardware architectures
13
- 风险成因何在?银行财会如何专业防范风险?-What causes the risk? Bank accounting to professional risk prevention?
vga_lcd_latest.tar
- vga lcd 控制器 24位VGA控制，支持12位DVI协议-This embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth. Making it compatible with almost
wola
- WOLA polyphase filter加权跌接累加FFT信道化技术-WOLA polyphase filter bank
bank
- 实现输入，输出显示的银行前台显示，并对输入进行检错输出-Realization of the input, the output shows the bank front display
reg_bank
- A register bank with the function of output=input when enable is true. Also having a reset function
Eight-cpu-design
- 单元电路的设计和元器件的选择 运算部件的设计 寄存器组的设计 指令寄存器的设计 程序计数器电路的设计 地址寄存器电路的设计 数据寄存器的设计 时序系统的设计 程序存储器的设计 输出寄存器的设计 微指令译码器的设计 微程序控制电路的设计 系统电路总图及原理 -Microinstruction translation of the design of the output re
SRAM
- 利用程序实现SRAM_读写测试，先进行初始化，读写操作，里面的页操作和bank操作。-Using program SRAM_, speaking, reading and writing tests, first initialized, read and write operations, the inside of the page and bank operation.
registerbank
- THIS file consists of register bank and its testbench
jpegencoder
- jpeg encoder in vhdl including modules MAC, Wavelet encoder, filter bank, image to text converter
romip2
- Rom design for filter Bank
ddr_sdram
- 包含ddr_sdr_conf_pkg.vhd，reset.vhd，ddr_dcm.vhd，user_if.vhd，ddr_sdram.vhd，Mt46v16m16.vhd以及仿真TB文件；设计采用Virtex ii系列芯片，DDR_SDRAM型号为Mt46v16m16，可用于进行DDR控制的初步学习使用；通过细致了解并进行逻辑控制，可深入理解DDR芯片内部构造； 支持133MHz系统时钟频率，突发长度为2，可进行读、写、NOP、激活、自刷新配置、预充电以及各ROW/BANK的激活改变等动作，较
syn6288
- 北京一家 语音芯的应用，例子，可以广泛用银行排队机，手持机的播报语音，交互仪器上语单播报等设备上(The application of a voice core in Beijing, for example, can be widely used in Bank Queuing machines, handheld broadcast voice, interactive instruments, unicast devices and other equipment)