搜索资源列表
niox
- Open source and clean clone of Altera NIOS-II Soft Processor. Not completed but some test do run ok.
DAC
- Quartus 9.0 Project of a dual DAC0808 interface.Very simple and clean design, plus Avalon slave interface!
keyscan3
- 键盘扫描 以及输入后在LED 上的显示数字是无人分配【是大牌fks东平干净哦耍大牌企鹅王如图七二五体弱配挖潜普通孤儿我陪你 -After scanning the keyboard and input on the LED display digital distribution is no big fks Dongping 【is clean and the king penguins Oh diva seven hundred twenty-five frail figure with
verilog1602
- 终于搞定了这个lcd液晶显示的程序，净是犯些不该犯的错误，还本人找了那么久，先是仿真查了所有时钟信号，又查了lcd_rs和lcd_rw，都没有错-Finally fix the LCD program, clean is a hideous make some stupid mistakes, I look for so long, the first looked up all the clock signal, and checked lcd_rs and lcd_rw, all not w
64
- 用vhdl写的4层楼电梯，功能强大，代码简洁！-Vhdl to write with four floors elevator, powerful, clean code!
digital-clock
- 此数字钟具有时，分，秒计时并显示功能； 2.能进行24/12小时制计时模块的切换； 3.具有校时，清除功能，能对时，分，秒进行调整； 4.具有整点报时功能：在59分51秒，59分53秒，59分55秒，59分57秒发出低音256HZ信号，在59分59秒发出一次高音1024HZ信号，音响持续一秒钟，在1024HZ音响结束时刻即为整点； -This digital clock with hours, minutes, seconds, chronograph and display
EDApingpongqiu
- 基于FPGA芯片，vhdl编写的乒乓球游戏，具有失球计数，指示乒乓球的方向，失球发声提示功能。-FPGA-based chip, vhdl writing table tennis game, with a clean sheet count, indicating the direction of table tennis, conceded voice prompts.
I2C_vhdl
- IMPORTANT NOTE: This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this signal can show noise effects whic
niosSDCARD
- This folder contains data for incremental compilation. The compiled_partitions sub-folder contains previous compilation results for each partition. contains previous compilation results for each partition.-As long as this folder is preserved,
PWM_Module
- Very clean design of a PWM module made in structural VHDL. Lower blocks are behavioral.Designed in Quartus 9.0,
USRP-PID-Controller-clean
- PID feedback controller project for USRP1 boards (FPGA with a convenient analog front manufactured by ettus research). Implements a bitstream as well as python-based user interface.
i2cBUS
- Altera的I2C总线FPGA程序，内有详细使用说明- The I2C Controller is available in VHDL and is optimized for the Altera® APEX™ , Stratix® , and Cyclone™ device families. All of the register addresses are defined as constants in the VHDL source
05448528
- s a clean renewable energy, wind energy draws more and more attention around the world. In case of high wind speed or low speed but substantial installed wind power capacity, wind turbine generators (WTGs) will take the place of traditional power