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cnt
- 俩个比较好的计数器的vhdl代码：一个是n位通用计数器，一个是的用到的语法比较全面。是比较好的学习资料-Both a relatively good counter VHDL code: one is the generic n-bit counter, one is the syntax used in the more comprehensive. Is a better learning materials
cnt
- 对输入时钟做除以8的分频和除以4的分频功能-Does the input clock frequency divided by 8 and divided by the number of sub-4 sub-frequency function
divNfreq
- 参数化分频器，以5为例，能很方便的扩展到参数N-osedge and negedge using common counter "cnt" parameter N is the double number of frequence division
t1
- 实现电机M/T法测速的VHDL代码，只要修改cnt值大小即可修改M/T法切换的频率，当小于cnt时为T法，大于时为M法。-Motor M/T method velocimetry of the VHDL code, as long as the modified value of cnt to modify the size of M/T method of frequency switching, when cnt is less than for the T method, for M gr
CNT
- 分频的VHDL语言描述，巨简单实用，一看就会，从2到16分频都有，好东西啊。-Sub-band descr iption of the VHDL language, giant simple and practical, one can see, from 2-16 pm band has, ah good things.
vhdl
- 当接收到一个信号(D_start)时，开始计时，再收到另一个信号(D_stop)时，计时结束，得到计时时间A，然后将时间A与给定时间B进行比较，如果小于时间B,程序结束，进行下一环节(LED)，否则返回重新等待计时(cnt:=0)-When receiving a signal (D_start), the start time, and then received another signal (D_stop), the time the end of time by time A, then
jishuqi
- 实现计数和分频，用于高精度频率计数器的设计，在一个模块内实现-frenquent cnt
chuan2bing
- Verilog语言实现的串行输出转换位并行输出的程序代码，并生成模块电路图-module b_c(dout,clk,clr,din) output dout input [3:0] din input clk,clr reg dout reg [3:0] q reg [1:0] cnt always@(posedge clk) begin cnt<=cnt+1 if(clr
cnt
- 在ise开发环境下，建立顶层模块和子模块的层次结构，其实现的功能是一个可复位课暂停开始继续的建议秒表-In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch