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dcm
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
my_dcm
- 在xilinx的ISE环境中配置一个DCM组件，可进行查看程序运行的时间。通过串口与终端设备相连
DCM
- ISE实现DCM组建例化，得到3倍频时钟-ISE to achieve established cases of DCM, received 3 octave clock
dcm_test2
- xilinx fpga 倍频的例子，包含整个工程， 如果去用ISE 实现倍频，dcm 用法-xilinx s FPGA dcm example
DCM
- xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
dcm2
- 基于Xilinx Vertex4的可综合的二级DCM模块源代码，可生成400Mhz时钟信号-Based on Xilinx Vertex4 of two integrated DCM module source code, can generate 400Mhz clock signal
BUFG_CLK2X_FB_SUBM
- xilinx DCM 应用的源代码，完全可用-xilinx DCM application source code, fully available
BUFG_CLK0_FB_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
BUFG_CLK0_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
BUFG_CLK2X_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
BUFG_CLKDV_SUBM
- xilinx DCM 应用程序，完全可用-xilinx DCM applications, fully available
xapp462_vhdl
- a example -Code for DCM in language VHDL-a example-Code for DCM in language VHDL
wtut_sc
- DCM includes a clock delay locked loop used to minimize clock skew for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X devices. DCM synchronizes the clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock
DCM_12M_1M
- xilinx下DCM输出12Mhz和1Mhz-Verilog DCM xilinx ISE
DCM_24M_20M_2M
- DCM实现24M 20M 2Mhz的输出-dcm、 verlig HDL、
dcm
- Xilinx的V4FPGA数字时钟管理模块的底层原语实现代码，硬件上跑通- The Xilinx V4FPGA digital clock administration module s first floor primitive realizes the code, on the hardware runs passes
DCM
- 详细介绍了基于XILINX公司FPGA时钟管理模块DCM的IP核生成和使用-xilinx ise DCM
dcm_IP
- 这是一个用verilog语言编写的程序，利用了自带的DCM IP核，可以做练习用-This is a program written in verilog using a built-in DCM IP core, you can do the exercises with...
DCM
- fpga DCM使用教程 好几个文档 帮助您一次学会使用DCM-fpga the DCM using the tutorial a few documents to help you first learn to use the DCM