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MDLS16265B_driver
- 液晶驱动程序，利用DP-FPGA与精电蓬远液晶MDLS16265B测试通过。-LCD driver, the use of DP - FPGA and Varitronix Peng Yuan LCD MDLS16265B test.
cf_dpsk.rar
- 用VHDl语言写的一个DPSK的调制和解调程序，该程序可以实现相对相位调制解调。可以运行在xilinx ISE 或者是QuartusII下。 ,VHDl written in a language with DPSK modulation and demodulation process, the program can be achieved relative phase modulation and demodulation. Can be run on xilinx ISE or Qua
DP
- TIC6000系列 C67浮点DSP处理器 派发站源代码-TIC6000 floating-point DSP processor series C67 station source code distributed
pll
- DPLL由 鉴相器、 模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低. -DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, sy
STDP602x-DP-HDMI-VGAtoLVDS
- Datasheet for Genesis Microchip STDP602x-DP,HDMI,VGAtoLVDS
dpll
- 本工程为锁相环，采用全数字系统设计，输出频率在10M~100M之间！可改进。-This project is phase-locked loop, all-digital system design, the output frequency between the 10M ~ 100M! Can be improved.
self_survey
- STEP7编程，可检测DP总线上模块的报错情况。-STEP7 program that can survey the models on DP bus and can indicate errors occured from models
dp
- datapath code in verilog for pipeline processor
Dip_PB_LED
- 4 bit counter. 1 Push Button (PB) and 1 Dip Switch (DP)are inputs. 4 Leds (common anode) are outputs.
verilog-pll
- 用verilog写的倍频电路 文件中介绍DP-The multiplier circuit file by verilog introduced DPLL
cell
- codes for DP ram synthesizable
Xilinx
- 2020 XILINX Vivado ISE IP License最全最可靠License获取方式。 LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MA