搜索资源列表
Viterbi_IP.rar
- viterbi译码器的IP核，可以直接编译使用,viterbi decoder IP core, the compiler can directly use
RSdecoder.rar
- cpld/fpga RS(204,188)译码器的verilog程序,cpld/fpga RS (204,188) decoder of the Verilog program
06-50.zip
- PAL decoder, spartan 3 FPGA,PAL decoder, spartan 3 FPGA
viterbi_for_bch.rar
- Viterbi based trellis decoder for (7,4) - binary BCH code,Viterbi based trellis decoder for (7,4)- binary BCH code
RS-decoder
- RS 解码器主要包括以下5 个主要部分：伴随式计算、计算错误位置和错误值多项式、 钱搜索计算错误位置、福尼算法计算错误值和纠正解码输出。-RS decoder includes the following five main parts: With style, calculated error location and error value polynomial, Calculated error location search of money
BCHencodeanddecode
- bch 编码和译码，用硬件语言vhdl实现-bch edcode and decoder
turbocodes_latest.tar
- turbo encode and decoder
viterbi
- verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Div3
- 一个除3器的Verilog源码，用于视频解码器的熵解码部分。纯组合逻辑，大小和加法器差不多。-In addition to device a Verilog source code 3, the video decoder for entropy decoding part. Pure combinational logic, about the size and adder.
decoder
- 指令译码器的设计vhdl语言或者verilog HDL语言对单片机程序的处理-Instruction decoder design vhdl language or verilog HDL language processing microcomputer programs
manchester-decoder-encoder
- Manchester Encoder - Decoder-Manchester Encoder- Decoder
c23_RS_decoder
- 精通verilog HDL语言编程源码9——RS(204,188)译码器的设计-Proficient in verilog HDL source programming language 9- RS (204188) decoder design
husw
- 用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Viterbi
- Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
3to8decoder
- 3 to 8 decoder is used to decode from 3 bit data to 8 bit data used in many applications
Decoder
- 这是一个HDB3的译码器，实现从HDB3双极性码到高低电平二值序列的转化-This is a decoder of the HDB3, HDB3 bipolar from high-low-level code to the conversion of binary sequences
decoder
- 一个verilog源代码，用于译码器的编程。-A verilog source code, for programming decoder.
PICC Modified-Miller Decoder
- Support 106/212/424/848kbps, modified miller code decoder. Si verified.
Program of 2 to 4 Decoder
- Verilog code for decoder