搜索资源列表
convolution_encoder_VHDL
- 卷积码编译码,由SERVICE、PSDU、TAIL和PAD域组成的DATA域应进行卷积编码,码率应根据所需的传输速率从R=1/2,2/3,3/4中选择-for 802.11a simulation WLAN FEC convolution_encoder g0=133 g1=171 Rate 0:1/2 1:2/3 2:3/4 for 802.11a simulation
FEC-in-DTV
- 数字电视信道编码xilinx资源,包括DVB-C,以及其他信道编码模块IP介绍-FEC solution in digital TV application
Lab4
- a transmitter and receiver with Humming FEC
fec
- RS编码电路 ,包括乘法器的模块和编码部分 RS编码器\mula_0.v RS编码器\mula_1.v RS编码器\rscode.v(The RS encoding circuit includes a multiplier module and an encoding section RS encoder \mula_0.v RS encoder, \mula_1.v, RS encoder, \rscode.v)
RTPPayloadFormatforReedSolomon
- ReedSolomon FEC used in RTP
