搜索资源列表
fpu_v18
- <Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.vhd pre_norm_mul.vhd mul_24.vhd vcom serial_mul.vhd post_norm_mul.vhd pre_norm_div.vhd serial_div.vhd post_norm_div.vhd pre_norm_s
fpu
- 利用FPGA实现浮点运算的verilog代码 希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help
fpu
- 使用VHDL语言描述的单精度浮点处理器。源代码来自国外网站。可实现单精度浮点数的加减乘运算。
fpu100_latest.tar
- 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in h
fpu100_latest.tar
- This a 32-bit floating point unit (FPU), which I developed in a project within the Vienna University of Technology. It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard-This is a 32-bit floating
PIDctrol
- VHDL实现PI控制,包括三个文件,FPU,PID-VHDL pi control，pid
FPU
- Verilog HDL code for implementation of double floating point architecture. Program takes care of diffent exceptions like overflow, underflow, NaN etc
fpu_v2_10_example_designs
- fpu example designs with VHDL
m10k_talk
- R10000 Superscalar Microprocessor nArchitecture of CPU and FPU nMemory Hierarchy nSystem Configuration nVerification and Design Methods
tiny64_latest.tar
- Descr iption Tiny64 A 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles. The word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also differnet word sizes. Due simpli
NU_fp_lib_original_modules_june_2002
- fpu unt which calcultes add sub div
fpu100_latest.tar
- Features - FPU supports the following arithmetic operations: - Add - Subtract - Multiply - Divide - Square Root
FPU
- 32位单精度浮点运算单元,遵从IEEE 754标准，持浮点加、减、乘、除等运算。-32-bit single-precision floating-point unit；comply with the IEEE 754 standard；support floating-point add, subtract, multiply operations.
faddsub
- FPU adder / subtractor it is confirmed to work at 32MHz by Spartan-6 SP605.
cores
- a core has been developed for your 32 bit fpu with a least 32x2 input 4 bit operator with round off and 32 bit output and 8 bit exeption data.
verilog_code_for_double_fpu
- 64位FPU，内含testbench，已经通过验证仿真。-64-bit FPU, embedded testbench, simulation has been validated.