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Fibonacci_sequence
- 用MATLAB 里的XILINX BLOCKS编写, 实现Fibonacci sequence算法, 当F为0时, 输出为0 F为1时, 输出为1 当F为N 时, 输出为F的N-1 加上 F的N-2.
Verilogexample
- verilog example 1.NAND Latch To Be Simulated.2.A 16-Bit Counter.3.A D-Type Edge-Triggered Flip Flop.4.A Clock For the Counter.5.The Top-Level Module of the Counter.6.The Counter Module Described With Behavioral Statements.7.Top Level of the Fibonacci
FIBONACC
- Program FIBONACCI. . Check this out, this is program in Pascal!
fibonacci
- it is a code to find fibonacci.
fibonacci
- source vhdl code implement Fibonacci series in hw
fibonacci_matlab_verilog
- 使用Matlab和Verilog实现fibonacci序列，包括源代码和testbench-use matlab and verilog to realize fibonacci sequence,including source code and testbench
crosstalkavoidance_vhdl
- this is crosstalk avoidance ieee 2009 code this contains binary code to fibonacci conversion code in encoder and fibonacci to binary conversion using states in decoder.-this is is crosstalk avoidance ieee 2009 code this contains binary code to fibona
Fibonacci
- Fibonacci数列的VHDL实现，程序细分为了各个模块实现了Fibonacci数列计算。Fibonacci数列：1,1,2,3，5，8...即当前元素为前两个元素之和。-Fibonacci sequence of VHDL, the program modules in order to achieve sub-Fibonacci series. Fibonacci numbers: 1,1,2,3,5,8 ... that is the current element and the fi
microFibo
- Fibonacci Series on Spartan d3
Fibonacci-Sequence
- Fibonacci Sequence VHDL code.
FIBONACCI_SERIES
- fibonacci series in vhdl
fib
- 一个基于VHDL编程的可用于FPGA实现的斐波那契数列计算器- implemented a circuit in VHDL that calculates Fibonacci numbers
VHDL-book3
- D_flipflop：1位D触发器的设计 D_fllipflop_behav：4位D触发器的设计 reg1bit：1位寄存器设计 reg4bit：4位寄存器设计 shiftreg4：一般移位寄存器的设计 ring_shiftreg4：环型移位寄存器的设计 debounce4：消抖电路的设计 clock_pulse：时钟脉冲电路的设计 count3bit_gate：3位计数器的设计 count3bit_behav：3位计数器的设计 mo
feibonaqi
- 斐波那契数列，用VErilog语言实现非常好-Fibonacci sequence, using VErilog language is very good ha ha ha ha ha ha ha
fibonaccicode
- verilog code for fibonacci codes
RAM
- 用verilog实现了IP核的使用，例化了一个RAM，用来进行读写操作，另外还编写了斐波那契数列来进行测试。-Using verilog to achieve the use of IP core, the instantiation of a RAM, used to read and write operations, in addition to the preparation of the Fibonacci sequence for testing.
Fibonacci
- （1） clkdiv 模块：对50MHz 系统时钟 进行分频，分别得到190Hz，3Hz 信号。190Hz 信号用于动态扫描模块位选信号，3Hz 信号用于fib 模块。 （2） fib 模块：依据实验原理所述Fibonacci 数列原理，用VHDL 语言实现数列 （3） binbcd14：实现二进制码到BCD 码的转换，用于数码管显示。 （4） x7segbc：采用动态扫描，使用4 位数码管依次显示Fibonacci 数列数据。 实验采用3Hz 频率来产生Fibonacci
AlteraLab1
- To design Fibonacci Sequence using Verilog. SOFTWARES USED: Xilinx Synthesis Tool ISE 9.2i INTRODUCTION. Hardware descr iption language (HDL) is a general-purpose language intended to describe circuits textually,
New folder
- verilog codes for counter,d flipflop,fibonacci series,prime numbers,top.