搜索资源列表
CPLD_CODE1
- ju继续上载CPLD的黄金参考源代码，希望对电子爱好者有所帮助-ju continue on the CPLD gold reference source, and I hope to help e-lovers
gold
- SRL16是Virtex器件中的一个移位寄存器查找表。它有4个输入用来选择输出序列的长度。使用XCV50-6器件实现，共占用5个Slice。用来生成gold码。-SRL16 Virtex devices is a shift register lookup table. It has four input used to select the output sequence length. Use XCV50-6 device, occupying a total of five Slice.
lcd_dsp
- verilog编写的串口和液晶驱动的程序。ＦＰＧＡ接收串口的数据，然后在液晶上显示，用的是黑金开发板。-verilog prepared by the serial and the LCD driver program. FPGA receives serial data, and then in the liquid crystal display, with the black gold development board.
NIOS
- 这是黑金动力社区FPGA开发板的源程序代码，前几天买个板子 光盘里带的-black gold FPGA source code
FPGA-pcb
- 黑金开发板的PCB布线。FPGA的板级布线说明图。-Black gold development board PCB layout. FPGA-board wiring illustration.
DEMO_V
- 黑金FPGA开发板（学生）测试程序 VHDL语言 包括led 按键 串口 lcd的检测-Black Gold FPGA development board (student) test procedures VHDL language, including the detection of serial lcd led key
Verilog
- 很不错的Verilog 书籍 ，包括ieee标准和黄金指南-Very good Verilog books, including ieee standards and Gold Guide
VHDL_GOLD_BOOK
- VHDL黄金宝典，VHDL设计的好助手，看看吧-VHDL GOLD BOOK,CLASSICAL RULL ABOUT THE VHDL DESIGN
gold_code_vhd_217
- Gold Code Generators in Virtex Devices
XAPP217
- Gold Code Generators in Virtex Devices
gold_code
- Gold code project with VHDL files
my_gold
- 基于FPGA的gold码发生器，用VHDL语言编写的源程序。-The gold code generator based on FPGA, VHDL language with the source.
1_hello
- 本例程为黑金fpga开发板作者的调试源代码，非常适合初学者设计的参考，与“nios2 那些事儿”教程配套。-The routines developed for the black gold fpga board of debugging source code, the reference design is suitable for beginners, and " nios2 that thing" tutorial package.
VHDL_learning
- VHDL学习资料，适合入门者快速提高，包括VHDL基本语句讲解，VHDL编程黄金宝典和100个VHDL设计范例。-VHDL learning materials, suitable for beginners to quickly improve, including statements to explain the basic VHDL, VHDL programming, and 100 Gold Collection VHDL design examples.
mcode_FPGA
- 伪随机码发生器，次源码已经经过了测试并通过时序仿真验证没有任何问题，此小m序列发生器的特征多项式我没有写，但我建议大家在看原代码之前还是先看下扩频通信中m、M、Gold序列的原理，只有这样才能够真正的明白伪随机码发生器发生器的原理。-mcode_FPGA
GOLD_VHDL
- 论文讨论的是基于VHDL 实现在系统编程平衡GOLD 码逻辑电路设计，给 出周期与相位可编程平衡GOLD 码生成电路设计方案。该方案由最长线性移位寄存器 与可选反馈支路构成。-Discussion paper is based on VHDL programming to achieve a balance in the system logic circuit design GOLD code given cycle and phase balance GOLD programmabl
programs_examples
- 黑金开发吧，EP2C8Q208的相关原理图，及各个工程，直接打开就可使用-Development of black gold bar, EP2C8Q208 related schematics, and various works can be used to directly open. .
gold_VHDL
- 一个用vhdl语言编写的程序，可以实现gold码的发生-A program using vhdl language, can the occurrence of gold codes
gold
- 基于vhdl语言的15位gold序列的设计的开端一部分程序-Vhdl language based on sequences of the 15 gold as part of the beginning of the design process
Black-gold-Sparten6_VerilogV1.6
- 黑金Sparten6开发板Verilog教程V1.6，黑金FPGA教程，多种实例讲解，非常经典实用。-Black Gold Spartan6 board Verilog tutorials V1.6, black gold FPGA course, a variety of examples to explain, very classic and practical.