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hdlc
- 该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码，会用QUATUSII的人都应该知道如何使用，希望能给你带来帮助-The project is based on the language verilog hdl frame transmission protocol HDLC frame of this generation - Codes will be used QUATUSII people should know how to use, in the hop
hdlc
- HDLC通信模块发送接收模块VHDL源码
HDLC_controller.rar
- a verilog code for hdlc controller,a verilog code for hdlc controller
trunk-hdlc.rar
- 高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
HDLC
- verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
hdlc
- 基于FPGA的HDLC协议控制器，能完成插零，删除0操作。-HDLC controller base on FPGA
hdlc_latest[1]
- HDLC解码控制，包括CRC校验，可以在一片3400A FPGA上实现8解码-HDLC decoding control, including the CRC check can be realized in a 3400A FPGA 8 decoding
hdlc
- HDLC接口协议的FPGA实现使用verilog-design of HDLC
hdlc
- HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
hdlc_decode
- 基于Verilog的HDLC解码器。其中时钟的提取采用数字锁相环-The HDLC decoder based on Verilog. Which are extracted using digital phase-locked loop clock
HDLC_g
- HDLC的一些相关文档，可能对HDLC设计有很大的帮助！-HDLC some relevant documents, HDLC design may be very helpful!
FPGAforDLC
- 采用Altera公司的FPGA芯片，在MAX+plus II软件平台上实现多路HDLC电路-Using Altera s FPGA chips, in MAX+ Plus II software platform to achieve multi-channel HDLC circuit
hdlc_1
- 高级链路控制的HDLC发送，写的还行，需要使用93版本的VHDL格式-Advanced Link Control HDLC to send, write that still need to use the 93 version of the VHDL format
LAOWAI
- 一个老外写的HDLC协议，包括说明文件，很有参考价值-Written by a foreigner HDLC protocols, including documentation, of great reference value
hdlc
- HDLC协议控制器，用FPGA实现的verilog源代码-HDLC protocol controller, implemented with FPGA verilog source code
FPGA-HDLC-design
- 基于FPGA的HDLC协议控制器的设计。FPGA-based HDLC protocol controller design. Pdf-FPGA-based HDLC protocol controller design. Pdf
dddddddHDLC
- FPGA的入门级资料 讲的很好 不错 hdlc的实现-fpga
hdlc_rs
- 一种带有CRC校验、一次可连续发送1－15块16字节数据、带有曼彻斯特码的hdlc收发程序，在Altera中仿真并在实际芯片中试验过的程序-One kind with a CRC check, send a continuous block of 16 bytes of data 1-15, with Manchester' s hdlc receive procedures in the Altera chip simulation and tested in the actual pr
HDLC
- HDLC 高级数据链路协议的源文件，用vhdl些的-HDLC 高级数据链路协议的源文件
HDLC协议接收文件
- HDLC协议接收文件，vhdl版本，适用于HDLC通讯协议