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70V631_VHDL_Model.zip
- 针对IDT公司71v631的fpga设计，VHDL语言模型。
IDTContrl
- 该Verilog程序提供了一种控制IDT系列Ram的读写操作程序，每次读写750个16位的数。-The Verilog program control IDT provides a series of read and write operating procedures Ram, 750 each to read and write the number 16.
70T633_VHDL
- idt 双口RAN 70t633 VHDL驱动-idt DUAL RAM 70t633 VHDL driver
IDT
- IDT频率综合器接口程序和应用实例，外加IDT的行为模型-IDT frequency synthesizer interface program and application examples, plus a behavioral model of the IDT
idt723641
- VERILOG双端口驱动IDT的双扣RAM很好用的-VERILOG Twill the IDT dual-port RAM drive good use