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xilinx_labs.tar
- quick start EDK xilinx labs
Labs
- verilog labs some helpfull basic taughts-verilog labs some helpfull basic taughts..
calibre_drc_lvs_data_2006.3.tar
- Calibre DRC and LVS labs.
e212a_laboratoare_xilinx
- there are some labs made by me .you will find her: a counter,a codificator,decodificator,and some others
lab_instructions1
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
lab_instructions2
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
lab_instructions3
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
Spartan-3ADSPs
- The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
lab1
- labs in verilog it consists of lab work from design of mux adders from primitives
XILINX_LABZ
- Xilinx labs which help in creating VHDL files for beginners.
Xilinx-labs-manual
- a Xilinx lab manual which contains sample codes and programming techniques which are used by beginners to learn VHDL
qdq_ise9migration
- 六人抢答器是旨在模仿答题抢答过程中选手抢答，答题倒计时，主持人控制以及数字清零等步骤。原则上算作是模拟仿真类动手实验，设计难点有筛选抢中的选手，抑制有选手违规抢答，主持人控制答题以及抢答时间，强中或者答题时间到的报警时间，以及在大屏幕上显示时钟倒计时以及抢中的选手编号并且对LED灯进行复位。-Six Responder is designed to mimic the answer in the answer in the answer in the process of players,
Synopsys_90nm_lib_course-OpenSPARC
- 开源可扩充处理器架构.源代码Synopsys_90nm_lib_course-OpenSPARC_labs_final_041509-Synopsys 90nm lib course-OpenSPARC labs final 041509
F06x_SMBus_EEPROM
- SMBus Routines for Silicon Labs C8051F06x with Serial EEPROM
labs_system_verilog_testbench
- system verilog testbench 对应代码。-labs for system verilog testbench
tp-vhdl
- A LOT OF LABS ON VHDL MADE AT SCHOOL BY my self A LOT OF LABS ON VHDL MADE AT SCHOOL BY my self
Seven_Segment_LED
- numato labs code , in verilog or in vhdl , which is very useful for small projects