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gongchengsheji-477
- 基于logmap算法的vhdl的实现。 通信系统的log—map算法数字vhdl的实现-logmap algorithm based on the achievement of VHDL. The communication system log-map algorithm to achieve the number of VHDL
NIOS_TFT
- 用Quartus II 8.0（32bit），NIOS编译环境下，用TFT做的一个数码相框，附加原理图和veri-log程序代码-Using Quartus II 8.0 (32bit), NIOS compiler environment, TFT do with a digital photo frame, attached schematic and program code veri-log
i2s_interface
- - I2S top level test bench. Two transmitters and two receivers are instantiated, one each in slave and master mode. Test result is displayed in the log window, there should be no errors.-- I2S top level test bench. Two transmitters and two receivers
checkNodee_Behavioral_VHDL
- LDPC码校验节点（checknode）进行奇偶校验方程时的vhdl编程，硬件语言实现-LDPC check nodes (checknode) carried out at the time of parity equation VHDL programming, hardware language
bitNode_Behaviora_VHDL
- LDPC码的消息节点（Bitnode）消息更新过程的VHDL语言实现-LDPC code of the message node (Bitnode) news update process of the VHDL language
33753129vhdl
- 对数计算源程序，能够在FPGA中计算某数的对数-Determined on the basis of the source, calculated in the FPGA to a certain number of log
memory
- the memory program are used to design the fpga application for in very log module
48_fir_4_tb
- fpga控制lcd1602的v-log源码-fpga control lcd1602 the v-log Source
48_fir_tb_1
- fpga控制lcd1602的v-log源码-fpga control lcd1602 the v-log Source
FINALAB
- it is veri log code for ALU comparator and shift register using veriwe-it is veri log code for ALU comparator and shift register using veriwell
liuy
- 一个精确时钟的v-log程序，只用一个全局时钟，增加了精确度-An accurate clock in the v-log program, only one global clock, increased accuracy
verilog_hjckzn
- Verilog 黄金参考指南是 Veri log 硬件描述语言及其语法 语义 合并以及将它应用到硬件设计的一个 简明的快速参考指南-Verilog Golden Reference Guide is Veri log hardware descr iption language and its syntax and semantics of merging hardware design to apply it to a concise Quick Reference Guide
vmm_log
- vmm log 验证平台，采用vmm搭建-vmm log verification platform, built by vmm
TAXI
- 基于VHDL的出租车计费器，通过VHDL语言来编程实现计费系统的四个功能块：分频模块，控制模块，计量模块和译码显示模块，最后使用MAX+PLUSII软件来对程序进行仿真，以模拟实现出租车的启动，停止以及等待等过程中的计时，计程和计费功能。-Taxi meter based on VHDL, VHDL language programming through the billing system of the four functional blocks: frequency module, co
exp_micro_s
- 自己在QuartusII9.1及Modelsim新版本中完成的microsequencer实例的工程文件。 1.echo uart,接收rx_data,再回复！ 2.运行时请注意完整路径： D:\EXP\EXP_SOPCbuilder\exp_micro_s 3.UART数据输入问题？ 3.1 MODELSIM中w完信号后，run/restart一次。 3.2 设置clock=20ns。 3.3 命令行中输入uart_drive调出uart_
altera_inspector.log
- vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL -code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
Alrera-FPGA-SOC-Cyclone-V
- Alrera FPGA SOC Cyclone V 官网开发板调试记录-Alrera FPGA SOC Cyclone V official website development board debug log
acs
- This an ACS unit which can be used in log-map algorithm as well as viterbi algorithm-This is an ACS unit which can be used in log-map algorithm as well as viterbi algorithm
altfp_log
- 浮点数 log运算模块 verilog语言编写 可直接调用-Log floating point arithmetic module can directly call verilog language
kaynak_kod_FPGA
- CODE TO CCD İ N VERİ LOG