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伪随机序列的说明和源代码
- 可控m序列产生器我分成四个小模块来做，M，M1，M2，M3分别对应为：m序列产生器、控制器、码长选择器、码速率选择器。-controllable m-sequence generator, I divided into four small modules do, M, M1, M2, M3, respectively : m-sequence generator, controller, code-selector, code rate selector.
div5
- 利用VHDL语言描述的5分频器（改变程序中m1,m2值，可作为任意奇数分频器）-The use of VHDL language is described in 5 prescaler (change procedure m1, m2 value, can be used as arbitrary odd prescaler)
XC4VLX60MB_Lab5_PROM_ISE91
- XCVLXMB the board Xilinx SRAM_BASED FPGA design is the main element Pieces, SRAM_BASED the FPGA, the design began to verify the results, may experience many changes, this time as long as the JTAG s DOWNLOAD CABLE with the IMPACT software is conti
Simply-RISC-M1-Core.tar
- Simply RISC M1 Core.tar
Cortex-M1
- Verilog Cortex-M1 source code