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目前以太网PHY芯片是通过总线MDC/MDIO
- 目前以太网PHY芯片是通过总线MDC/MDIO，但是基本上是通过MAC芯片直接管理的，本代码实现了通过FPGA管理PHY。即由FPGA完成MII管理,At present, Ethernet PHY chip through the bus MDC/MDIO, but basically through the direct management of MAC chip, the code through the FPGA implementation management PHY. FPGA
mdio
- MDIO verilog RTL代码，SOC可以通过MDIO接口来访问外部PHY等慢速外设-MDIO verilog RTL code
mdio
- cpu与phy通信，让cpu能读写phy芯片，实现通信-cpu communication with phy
mdio_slave
- It s VERILOG (not VHDL) code for mdio slave
MDIO
- 网络PHY88E1111的 寄存器 通讯协议的 verilog描述 能实现 lookback 能读出PHY的资料-The register communication protocol Verilog descr iption of the network PHY88E1111 lookback can read the PHY data
mdio_mdc
- mdio verilog 实现-mdio verilog coding
mdio_slave_interface
- Management Data Input/Output Interfaces, or MDIO, are specified in the IEEE 802.3 standard. Their primary application is to provide a Serial Management Interface (SMI) to transfer management data between an Ethernet Media Access Controller (MAC)
mdi_o
- 这个是mdio的源码程序，可以拿来直接用-this is mdio program
mdio_vhdl
- mdio slave code with state machine
udp_send1
- 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output
mdc
- 实现对MDIO通信接口的MDC主机时钟进行整形，输出占空比50 的时钟方波-MDIO communication interface to achieve the MDC host clock shaping, the output duty cycle of 50 of the clock Fang Bo
mdio
- 用VIVADO软件编写的，实现以太网芯片88E1510中的mdio控制模块代码，并且含有VIO仿真文件-Written in VIVADO software, the realization of the Ethernet chip 88 e1510 mdio control module of code, and contains the VIO simulation file
mdio
- mdio的读写操作实例代码，实例代码为操作phy芯片的流程(the code of mdio,including reading and writing the code of mdio)
sim
- 调试bcm5396，写入和读取内部寄存器功能。功能验证可以用(Debug bcm5396, write and read the internal register function. Functional validation can be used)
以太网MDIO接口
- 以太网的mac层与phy芯片之间的mdio接口通信，现已在lattice环境验证通过。