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key_scan
- 程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描，简洁明了，通俗易懂，比较适合VHDL初学者-procedure was used in hardware descr iption language (VHDL) to achieve : 4 * 4 keyboard scan, concise, easily understood and more suitable for beginners VHDL
anjian
- 按键输入模块（key）： --可编程延时发生器（数字同步机）的前端输入模块：0－9十个数字键按键输入模块原型 --前端模块：消抖 --对i0－i9十个输入端的两点要求： --（1）输入端要保证一段时间的稳定高电平 --（2）不能同时按下两个或多于两个的键 --后级模块：1、编码；2、可变模计数器 --编码模块：8线－4线（0－8 BCD码） --可变模计数器模块：以编码模块输出的32位BCD码为模值-button input module (key) : -- p
VHDL语言100例详解
- VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructu
32位-33M 从模式(target)PCI接口参考设计_lattice
- 32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考-32 / route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
4bits_alu
- 实现4位加减乘除的alu，采用超前进位加法和布斯乘法，代码较为简单。-achieve four of the ALU arithmetic using CLA Bush and multiplication, code more simple.
32fenpinqi
- 这是用VHDL语言写的32位分频器的程序，可直接运行，看结果，欢迎使用。多指正，交流。-This is written in VHDL 32 dividers procedures can be run directly see the results, welcomed the use. More correct exchange.
state_classic
- 用VHDL语言编写的语言,可以利用MODELSIM进行仿真.对于初学者,则更有参考价值.-prepared using the VHDL language, we can use MODELSIM simulation. For beginners, the more valuable reference.
TI6713DSKVHDL
- TI6713浮点DSP的DSK的VHDL。比较全面。可以编译运行。-TI6713 floating-point DSP DSK VHDL. More comprehensive. Compiler can run.
automachine
- 自动售货机 l 设计要求： 1．机器有一个投币孔，每次只能投入一枚硬币，但可以连续投入多枚硬币。机器能识别的硬币金额为1元，5角和1角。顾客可选择的饮料价格有1元，1元5角，2元三种。每次只能售出1瓶饮料。 2．购买饮料时先选择饮料价格再投币，当投入的硬币总金额达到或超过饮料价格后，机器发出指示信号并拒收继续投入的硬币。顾客投币后，按动确定键，机器将发出饮料和找零硬币，若所投金额不足，则发出欠资信号指示。在欠资情况下，顾客可以继续投币购买，也可按取消键，机器将退出所投入的全部金额。
statemachine
- 自己做的一个关于more状态机的三种描述的比较。以后会有更多的资料，请大家关注。-doing more of a state machine on the three described earlier. Many more information, please everyone's attention.
Cpu_model
- Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic
binary2bcd
- This build is for developing a \"binary-to-BCD\" converter for use in // displaying numerals in base-10 so that people can read and interpret the // numbers more readily than they could if the numbers were displayed in // binary or hexadecimal
system_c
- system c 是在C环境下的硬件描述语言,比VHDL 等语言具有更强的抽象能力,内有system C的开发支持库和一些VC下的开发例程-system in the C environment hardware descr iption language, than languages such as VHDL is more abstract, C within a system to support the development of the VC and some routines u
Seg_HLD3Core(400)_(C)
- 这是非常好的vhdl例子，大家看看吧，希望与大家分享更多的好东西-It is a very good vhdl example, we look at it, and we hope to share more good things
Music_HLD3Core(400)_(C)
- 这是非常好的vhdl例子，大家看看吧，希望与大家分享更多的好东西-It is a very good vhdl example, we look at it, and we hope to share more good things
SN7448
- 这是非常好的vhdl例子，大家看看吧，希望与大家分享更多的好东西-It is a very good vhdl example, we look at it, and we hope to share more good things
bin2bcd7
- 这是非常好的vhdl例子，大家看看吧，希望与大家分享更多的好东西-It is a very good vhdl example, we look at it, and we hope to share more good things
veriexamples
- 非常多的verilog实例，对于刚入门者比较有用-lot of verilog example, just beginners more useful
more
- more状态机.有自起动,功能.出错自检,通过验证-more state
2-more-than-one-way-selector
- 利用FPGA编程-------实现“ 2选1 多路选择器”-2 more than one way selector