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modu
- this the verilog code that performs the modulus function ... most importantly it is synthesisable... uses the repeated sub algorithm-this is the verilog code that performs the modulus function ... most importantly it is synthesisable... uses the repe
ModifyInstruction
- 数字环路滤波器是由变模可逆计数器构成的。 该计数器设计为一个17 位可编程(可变模数) 可逆 计数器,计数范围是,由外部置数DCBA 控制-Digital loop filter is composed of variable-mode reversible counter. The counter is designed to a 17-bit programmable (variable modulus) reversible counter, counting range is s
parall_ad_da
- 在和众达SEED—XDTK平台上，基于XC4VSX25的 平行模数，数模转换程序-In and Jones SEED-XDTK platform, based on the parallel XC4VSX25 modulus, digital-analog conversion process
pll
- DPLL由 鉴相器、 模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低. -DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, sy
321
- VHDL模为10，范围为0-9，可变模计数器是指计数／模值可根据需要进行变化的计数器。-VHDL model of 10, the range of 0-9, the variable modulus counter is counting/A value can be changed as needed counter.
Intelligent-modulus-DPLL-control-design-and-analys
- 智能模值控制的数字锁相环的FPGA设计与分析Intelligent modulus DPLL control design and analysis of FPGA-Intelligent modulus DPLL control design and analysis of FPGA
count
- 基于FPGA的可变模的计数器，计数器，加法-FPGA-based variable modulus counter, counter, addition
variabled-counter
- 这是一个变模计数器的vhdl程序，可以实现模值为9、11、13、15的计数功能。-This is a variable modulus counter vhdl program value 9,11,13,15 counting function can be achieved mold.
A-4-bit-variable-modulus-counter
- 用Verilog HDL设计一个4bit变模计数器和一个5bit二进制加法器。在4bit输入cipher的控制下，实现同步模5、模8、模10、模12及用任务调用语句实现的5bit二进制加法器，计数器具有同步清零和暂停计数的功能。主频为50MHz，要求显示频率为1Hz。-A 4-bit variable modulus counter and a 5bit of binary adder using Verilog HDL design. 4bit input under the control
god
- This paper presents a novel robust number theoretic transform called inverse Gray Robust Symmetrical Number System (IGRSNS) and proposes its application for CDMA systems. The transceiver structure for three moduli IGRSNS-CDMA with one redunda
count
- 各种常用计数器模块，加减可控计数器和模可变计数器等等，经过仿真得到了正确的波形-Various common counter module, subtraction controllable variable modulus counter counter and so on, through simulation to get the correct waveform
prng
- 采用线性同余法的素数模乘同余发生器产生随机数,采用5级流水线设计-Using a linear congruential method prime modulus multiplicative congruential random number generator, using five pipeline design
15_tlc5620dac
- 利用状态机实现对tlc5620dac控制，实验时按key1,可选择DAC的通道，数码管1显示，按key2，key3可 输入8位数/模转换值，由数码管3，4显示，按key4，选择输出电压模式，由数码管8显示，0表示1倍，1表示2倍，按key5,将当前数据发送到DAC模块启动一次DA转换，这时可以万用表测量输出，也可以与理论值做下比较。-When using state machine to control the tlc5620dac, experiment by key1, choice o
m60v20161109
- 用verilog语言实现的模为60的计数器，经编译合格，利用quarter2及以上可以直接使用(Using Verilog language to achieve the modulus of 60 counters, compiled by qualified, using quarter2 and above can be used directly)
m60component20161109
- 用verilog语言实现的模为60的计数器，经编译合格，利用quarter2及以上可以直接使用，并使用了分块模式(Using Verilog language to achieve the modulus of 60 counters, compiled by qualified, using quarter2 and above can be used directly, and the use of sub block mode)