搜索资源列表
xapp336_8b10b
- 可编程器件大厂Xilinx提供的高速多状态编码8b_10b编码器，可直接使用在Xilinx公司器件的设计上-Xilinx programmable device manufacturers to provide high-speed multi-state coding 8b_10b encoder, direct access to the Xilinx devices on the design
digitalsystemDesign
- 第7章数字系统设计实例 7.1 半整数分频器的设计 7.2 音乐发生器 7.3 2FSK/2PSK信号产生器 7.4 实用多功能电子表 7.5 交通灯控制器 7.6 数字频率计-Chapter 7 Digital System Design Example 7.1-integer dividers designed Music Generator 7.2 7.3 2F SK/2PSK Signal Generator 7.4 Table practical multi-f
wave_gen
- 波形发生器，带TESTBENCH， 多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH.
CPU
- 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
multi
- 实现了三种乘法器，可以进行性能比较，比较有较之-multi
Multi_function_waveform_generator
- 多功能波形发生器VHDL程序与仿真.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成各种波形的线形叠加输出。 -Multi-function waveform generator and simulation of VHDL procedures. The realization of four kinds of common sine wave, triangle, sawtooth, squ
multi-functional_digital_clock
- 基于verilog的多功能数字钟，内含各功能模块-Verilog-based multi-functional digital clock that contains the function module
Multi-agent_app
- This the first part of a two-part paper that has arisen from the work of the IEEE Power Engineering Society’s Multi-Agent Systems (MAS) Working Group.-This is the first part of a two-part paper that has arisen from the work of the IEEE Power Engine
lcd_time
- 一个基于VHDL的多功能数字钟设计，能在LCD上显示时间，调整时间，整点报时，音乐为美妙的梁祝。-A VHDL-based design of multi-functional digital clock that can display time in the LCD, adjust the time, the whole point of time, music was wonderful Butterfly Lovers.
multi-function_waveform_generator
- 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 -4 sine wave to achieve common, triangle, sawtooth, square wave (A, B) the frequency and amplitude controlled output (square wave- A duty cycle is contr
multi-cycle-MIPS
- multicycle-MIPS verilog implementation
multi-clock-design
- FPGA 多时钟系统设计的简介。文章介绍了多种多时钟的设计的方案。-FPGA introduction to multi-clock system design. This paper introduces the design of a variety of multi-clock scheme.
VHDL-multi-function-clock
- 多功能时钟,包括一个时钟和一个秒表,可以互相切换并且不过中断各自的运行-a multi-function clock
Multi-functional-digital-clock
- 多功能数字时钟 时钟显示 手动计时 整点报时-Multi-functional digital clock Clock display Manual timing Hourly Chime
Multi-function-digital-clock
- 多功能数字钟，包含时钟，倒计时，秒表-Multi-function digital clock
Multi-decoder
- Quartus环境下多路选择器的编写代码，适合初学数字逻辑设计的进行学习-Multi-decoder in Quartus
MIPS-multi-cycle-(Quarters-II--Verillig)
- Multi cycle MIPS processor verilog
multi-function-digital-clock
- 基于fpga的多功能数字时钟设计，有预设和报警功能-Fpga-based design of multi-function digital clock, presets and alarm functions
multi-CPU
- Verilog开发的能下载到FPGA实验板上运行的多周期CPU-Verilog can be downloaded to the FPGA development board running experiments multi-cycle CPU
VHDL-Multi-fuction-Clock
- 设计一个多功能数字钟，要求显示格式为小时－分钟－秒钟，整点报时，报时时间为10 秒，即从整点前10 秒钟开始进行报时提示，喇叭开始发声，直到过整点时，在整点前5 秒LED 开始闪烁，过整点后，停止闪烁。系统时钟选择时钟模块的10KHz，要得到1Hz 时钟信号，必须对系统时钟进行10,000次分频。调整时间的的按键用按键模块的S1 和S2，S1 调节小时，每按下一次，小时增加一个小时，S2 调整分钟，每按下一次，分钟增加一分钟。另外用S8 按键作为系统时钟复位，复位后全部显示00－00－00。-T