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靳远－源程序
- 几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
dianzizhong
- 这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!-This is my learning process in the middle of the 10-minute program, containing various clock module and the counter, accumulator, and can download, compile!
wave_sin_fangbo
- VHDL小程序（本人的一些小成绩哦，希望对大家有帮助）-VHDL small programs (some of my small achievements Oh, we want to help)
用VHDL实现布斯算法
- 这个例子是讲述用VHDL实现布斯算法，应该有点用，是我的研究生师哥给我的。-this case is about the use of VHDL Booth algorithm, should use a bit of my graduate students Shige to me.
unicntr
- 通用寄存器的部分代码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY traffic IS PORT(clk,sm,sb:IN bit mr,my,mg,br,by,bg:OUT bit ) END traffic -part of the general purpose registers IEEE code LIBRARY USE traffic IEEE.STD_LOGIC_1164
ddfs
- 我自己用vhdl实现编的dds，能实现正弦波，方波，三角波。-my own use VHDL to achieve series dds, able sine, square, triangle wave.
zishiyingfenpin
- 我的学习经验，一种自适应分频及分频方法的实现，很好用的哦-my learning experience, an adaptive frequency-frequency method and the realization of the good, oh
simplevhdl
- 我是VHDL的初学者，这是我自己编译的简单的几个VHDL码，功能有3-8解码器及其testbench,16位寄存器及其testbench和交通灯。 希望能和其他初学者一起讨论学习，并得到高手的指点-I VHDL beginners, this is my own translation of a few simple VHDL code. 3 -8 function decoder and testbench, 16 Register and testbench and traffic li
dpram_fpga
- 这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
sdram_control
- 这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com
sanfenpin
- 这是我自己编写的三分频，也就是奇数分频，占空比为1：1，当然如果需要其它奇数分频，只要将程序里面的N和counter修改即可-This was my third prepared by the frequency, which is odd hours, frequency and duty ratio of 1:1. Of course, if the needs of other odd hours, frequency, as long as the proceedings inside
SimpleRAMModel
- 一个SIMPLE RAM ACCESS的VHDL很经典的例子，我老师的作品。-a SIMPLE RAM ACCESS VHDL classic example of my teacher's work.
HXRJTD
- 这是本人在Max plus2环境下用VHDL语言编的交通灯控制程序。做EDA课程设计的朋友可以下来参考参考。-This is my Max plus2 environment with VHDL addendum to the traffic lights control procedures. EDA design courses so friends from the reference reference.
fpgadigitalclock
- My thesis entitled \"fpga digital clock,\" immature, to enlighten -My thesis entitled "fpga digital clock, "immature, to enlighten
MyClockTest
- 这是我电子线路测试的作业，在FPGA板上实现数字钟，（Max2环境）采用VHDL语言编写，非常适合初学者。具备24小时计时，校时，低高音整点报时，定时和多重功能选择的功能。-This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time,
ft_top
- 用quartus6原理编辑方式写的简易频率计我自己的实验来的 保证能使请您认真查看谢谢 -quartus6 principle used to write the editorial summary Cymometer my own experiments can guarantee you Thank you seriously View
sobel
- 这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合和仿真，并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测，同时还可以实现其它的图像模块化处理算法，例如高斯滤波，平滑等。-this is my own preparation for the 256 * 256 size of the image segmentation Edge Detection vhd document in the n
ISA.rar
- pc104代码，这是本人调通过的。标准ISA通信接口，用VHDL编写,pc104 code, This is my tune adopted. ISA standard communication interface, using VHDL prepared
KCPSM3.rar
- 这个是在网上下载的picoblaze的资料，里面有些我自己写的使用方法，现在把它上传给大家。如果有需要的可以下载。个人感觉这个8位的软核开发起来有点麻烦，但是使用起来还是很好用的。对于其中的代码，归原作者所有。,This is the picoblaze downloading information, which some use to write my own methods, now upload it to you. If there is a need can be downloade
MY
- my work in the acedemic-my work in the acedemic...