搜索资源列表
ml505_mig_design
- Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1-Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1
crc16_d64_tx
- 一个在SRIO中使用的CRC校验代码，非常好用-The code is used for SRIO
SRIO-phy-code
- SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考-SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development
pg007_srio_gen2
- FPGA手册，xilinx 的srio官方手册，仔细阅读(FPGA manual, Xilinx sRIO official manual, read carefully)
Vivado 2016.4 SRIO License
- Vivado 2016.4 SRIO License,已经在Vivado 2016.4 测试通过，可以生产位流。其他版本没有测试，估计也是可以用的(Vivado 2016.4 SRIO License, which has been passed in the Vivado 2016.4 test, can produce a bit stream. The other versions are not tested, and the estimates are also available.)
SRIO_DSP_X1
- xilinx 7 系列fpga与dsp srio数据传输(fpga and dsp communation with srio)