一个SDH中最基本传输模块STM-1的帧头检测器，verilog编程实现

用verilog语言设计一个二进制序列检测电路， 当输入有连续“1011”出现时有输出为‘1’， 否则为‘0’.-Verilog language used to design a binary sequence detection circuit, a continuous input " 1011" appears when the output is ' 1 ' , otherwise ' 0' .

Module that can shift stream by one or more bits. It can be use for sinhronization in STM.

stm 32 key 键盘搜索 键盘应用单片机开发-stm 32 key