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vhdl_traffic
- 模拟交通灯实验 模拟路口的红黄绿交通灯的变化过程，用LED 灯表示交通灯，并在数码管上显示当 前状态剩余时间。-simulation experiment simulated traffic lights junction of red, yellow, and green traffic lights to the process of change, said LED lights for traffic lights, and the digital tube display th
leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOT
xapp134_vhdl
- The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with timing constraints at 115 MHZ.
uart_vhdl_lattice
- lattice的串口仿真的程序- serial port simulated programme of lattice
FIR低通滤波器部分模块
- 一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with -30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
division_A.rar
- 正交方波信号的四细分功能，含有仿真波形。用于光栅信号的四倍细分。,Orthogonal square wave signal a breakdown of the four functions, containing simulated waveform. Grating signal for four times the breakdown.
web_cpu88.zip
- Intel微处理器8088的VHDL实现，可以用ModelSim进行仿真测试。,Realization of intel microprocessor 8088 in VHDL language, and can be tested and simulated with ModelSim.
DW8051.rar
- Synopsys 公司的DW8051源代码，用verilog编写的，代码很完整，可以仿真，对采用8051核做嵌入式的人很有帮助,Synopsys company DW8051 source code, written with Verilog, the code is complete, can be simulated using 8051 nuclear helpful people who do Embedded
verilog_sdram_controller_testbench
- SDRAM 控制器 ，Verilog版本的，带有完整的SDRAM 仿真模型，testbench等，能够实际使用，并且利于学习-The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz
shipintuxiang
- 基于VHDL，实现视频图像的行列计数器，已经调试仿真通过可用.-Based on VHDL, the ranks of video image counter, has been simulated through the available debugging.
heartbeat
- 用VHDL编译的源代码，模拟心脏跳动，解压后直接用Quartus打开project即可，不好意思刚才第一个那个模拟心脏跳动（heartbeat）的源程序发错了，请删除，-Compiled with VHDL source code to simulate the beating heart, after extracting the direct use of Quartus can open the project, I am sorry but the first one that simu
stamp_seller
- 一个自动售邮票的控制电路。 用两个发光二极管分别模拟售出面值为六角和八角的邮票，购买者可以通过开关选择一种面值的邮票，灯亮时表示邮票售出。用开关分别模拟一角、五角和一元硬币投入。用发光二极管分别代表找回剩余的硬币。 要求：每次只能售出一枚邮票；当所投硬币达到或超过购买者所选面值时，售出一枚邮票，并找回剩余的硬币回到初始状态；当所投硬币值不足面值时，可以通过一个复位键退回所投硬币，回到初始状态。-An automatic control circuit sell stamps. With
song
- 歌曲是什么名字我忘了，代码仅提供一个用verilog编写音乐的模板，想编写什么音乐就往里边套用格式就行了。 本程序无法用软件实现仿真音乐效果，当然可以仿真波形输出，真实音乐效果需用开发板仿真才行，所以就不附仿真图了 用quartus2软件打开即可。 -What are the names of songs I forgot, the code with verilog only prepared to provide a template for the music, what mu
Counter_VhdlCode
- it is a simple counter written in vhdl , can be simulated using model sim worked on xillinx for fpga.
ADControl
- 用verilog实现，ADC控制，源代码，可进行仿真-Verilog with the realization of, ADC control, source code, can be simulated
vhdl
- ：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。-: A Shanghai taxi meter area for example, the use of Veri
PROJ
- 1、本实验模拟正弦函数发生器 2、使用逻辑分析仪查看波形 3、/proj/simulation目录中可以在modelsim中仿真-1, this experiment simulated sine function generator 2, using the logic analyzer to view waveform 3,/proj/simulation directory of simulation in modelsim
PLDsystemcode
- 有关温度传感的VHDL程序，有数字测量还有模拟测量，还有课件可参考-VHDL-related procedures of temperature sensing, and measuring the number of measurements are simulated, as well as courseware can be found
FIR
- The FIR digital filter algorithm is simulated and synthesized using VHDL
traffic_light
- this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit]. -this project is traffic lights on fpga. ı used xilinx ise and simulated modelsim. [used spartan 3e development kit].