搜索资源列表
timers.pspice
- PSpice model for 555 timer
8051IP
- 8051的IP,采用VHDL语言描述,支持intel的HEX格式,包括中断,定时器等.-8051 IP, the use of VHDL language descr iption, support intel s HEX format, including the interruption, such as timers.
Digital_Clock_VHDL
- 使用VHDL开发的简易数字时钟软件，可以作为初学者熟悉定时器应用的实例程序。-Use VHDL to develop a simple digital clock software can be used as timers for beginners familiar with examples of the application process.
aludesign
- In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmatic and logical operations. The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one
Microwave_timer
- 此代码可以实现微波炉定时器的功能。经过验证。-Microwave oven timers
C8051F530A-Timers
- C8051F530A的计数器程序，包括计时器初始化、中断程序、控制方法等。-C8051F530A counter procedures, including the timer initialization, interrupt procedures, control methods.
alu
- In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit (CPU) of a computer, and even the simplest microprocessors conta
17-Timers
- C8051F040的TIMER可编程计数器的程序，经调试通过-C8051F040 process the TIMER programmable counter, the debugging
logic
- Verilog HDL逻辑与计算机设计基础实验全部试验报告，包括寄存器，定时器，全加器，同步时序电路，译码器等的实验。-Verilog HDL logic and computer design basic experiment all test reports, including registers, timers, full adder, synchronous sequential circuits, decoders and other experiments.
trafficlight
- 基于VHDL的十字路*通灯控制系统设计与实现,定时器模块由25S、5S、20S三个定时器组成，分别确定相应信号灯亮的时间。三个定时器采用以秒脉冲为时钟的计数器实现。eg、ey、er分别是三个定时器的工作使能信号，tm25、tm5、tm20是三个定时器的计数结束指示信号。 控制模块是对系统工作状态的转换进行控制，根据交通规则可得系统状态转换情况。ar、ay、ag br、by、bg分别表示由控制器输出的A道和B道的红、黄、绿信号灯亮的时间；eg、ey、er分别表示由控制器输出的控制25S、5S
RTThread_uart1
- RTSTREAD实现功能: 利用通用定时器实现定时加一-RTSTREAD functions: the use of general-purpose timers to achieve timing plus a
Amber_ARM-compatible_core_latest.tar
- The Amber processor core is an ARM-compatible 32-bit RISC processor. The Amber core is fully compatible with the ARM ® v2a instruction set architecture (ISA) and is therefore supported by the GNU toolset. This older version of the ARM instr
CycloneIII_EP3C40F780C8_6_Timers
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,定时器实验代码-SOPC,CycloneIII，EP3C40F780C8，timers code
timer
- 基于fpga的定时器，嵌入式开发，调试通过-Fpga-based timers, embedded development, debugging through. .
fpga_timer_good
- 基于fpga的飓风4系类的定时器，嵌入式开发，调试通过。-Fpga-based hurricane category 4 system timers, embedded development, debugging through.
zyplj
- 采用EDA技术，使用Quartus2软件完成了数字频率计的设计与实现，其中包含计时器，控制器的设计，很实用-Using EDA technology, the use of software to complete Quartus2 digital frequency meter design and implementation, which includes timers, controller design, very practical
Timers
- vhdl code for Timers in 8051
clock_fpga
- 基于VHDL的FPGA设计，设计一款多功能的电子定时器，包括计时跟倒计时。-VHDL-based FPGA design, design a versatile electronic timers, including the timing with the countdown.
8051_cpu_verilog
- The 8051 microcontroller is member of MCS-51 family, originally designed in the 1980 s by Intel. The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system products. The basic
timer
- 基于VHDL语言的一个简单秒表，包含按键消抖模块、数码管译码、计时器等模块。直接适用于basys2和nexys3两个开发板。更改ucf文件后适用于其他开发板-A simple stopwatch based on VHDL, including key debounce module, digital decoder, timers and other modules. Directly applicable to basys2 and nexys3 two development boards