搜索资源列表
DesignCompiler
- Design Compiler使用简要说明,说明了用这一工具进行综合的过程 -use Design Compiler brief statement, the use of this tool for integrated process
WinFilter08
- WinFilter is a software tool provided as freeware to design digital filter.-WinFilter is a software tool provided as fr eeware to design digital filter.
dianti.rar
- 以FPGA技术为基础，以VHDL为语言，以QuartusII为工具，设计一个5层楼的电梯控制器,To FPGA technology, to VHDL language to QuartusII as a tool to design a 5-story elevator controller
VHDLRS232_RS422.rar
- VHDL写的RS232和RS485通信代码,很基础的一个工具,VHDL written RS232 and RS485 communication code, it is a tool based on
debussy
- Debussy 是NOVAS Software, Inc(思源科技)发展的HDL Debug & Analysis tool，这套软体主要不是用来跑模拟或看波形，它最强大的功能是：能够在HDL source code、schematic diagram、waveform、state bubble diagram之间，即时做trace，协助工程师debug。 本文主要是介绍Debussy的使用，以及如何在Modelsim环境下生成Debussy所需要的fsdb文件-user guide f
ADC0832_test.rar
- ADC0832是一个8-bit的ADC转化芯片，工作频率为250Khz，最大频率可达400Khz，转化通道有两个，输入电压可分有单端或差分形式。本测试使用单端电压输入形式，从昔年的CH0输入电压，使用Xilinx XC3S200AN开发板，并且使用Xilinx ise工具中的ChipScope工具来查看转化后的DO数据是否正确。经验证，输入电压范围是0V--5.5V,当电压达到5.5V时，满刻度.,ADC0832 is an 8-bit conversion of the ADC chip, t
nlint-user-manual nlint verilog vhdl 规则库
- nlint verilog vhdl 规则库 支持自定义 批量检查代码中bug -nlint a eda debug tool software rules ， user define rules ， verify code automatic
mcpu_1.06b
- MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source
fizzim_4.41
- FSM generation tool, exciting one
DCM
- xilinx SP605开发板的DCM模块验证程序，coreGen工具生成DCM核，由DCM完成时钟分频、倍频、移相等操作-xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
modelsim
- 这是一个关于仿真工具MODELSIM的安装和使用。-This is a ModelSim simulation tool on the installation and use.
VHDLtraining
- 这是一个好的学习VHDL语言的工具，全动画演示-This is a good tool to learn VHDL language, all-animated demo
P8051
- This a FREE tool chain which compiles C codes into 8051 binary code, converts the binary to RTL ROM, and simulate in Modelsim. SDCC is the compiler. Example compilation: cd compile sdcc --iram-size 0x80 --xram-size 0x800 t8051.c RE
VHDL_USERGUIDE
- 本书的主要的服务对象是熟悉硬件系统，而对软件的设计经验缺乏的工程师；叙述了VHDL的用法-This guide is intended for the engineer who is familiar with the principles of hardware design, but has little experience in designing with a language-based synthesis system. It describes the general c
plj
- 数字频率计是一种用来测试周期性变化信号工作频率的装置。其原理是在规定的单位时间（闸门时间）内，记录输入的脉冲的个数。我们可以通过改变记录脉冲的闸门时间来切换测频量程。本文利用EDA技术中的Max+plusⅡ作为开发工具,设计了基于FPGA的8位十进制频率计,并下载到在系统可编程实验板的EPF10K20TC144-4器件中测试实现了其功能。-Digital frequency meter is a kind of cyclical changes in the signal used to tes
quartus2
- quartus工具入门文档，altera公司官方软件翻译全文。-tool for quartus entry documents, altera company official translation of the full text of the software.
A_bit_serial_data_transmitter
- 比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify th
TRL_Design_of_a_asynchronous_bit_serial_data_trans
- RTL 异步数据传送模块 用verilog HDL 语言描述 输入为八比特数据，执行操作后异步每比特输出。-• To create Verilog-HDL module written in the RTL style appropriate for both simulation and synthesis, for an Asynchronous Serial Data Transmitter. • To verify the correct behavi
FPGA_SPI_FLASH
- 本应用指南讲述 Spartan-3E 系列中的串行外设接口 (SPI) 配置模式。SPI 配置模式拓宽了 SpartanTM-3E 设计人员可以使用的配置解决方案。SPI Flash 存储器件引脚少、封装外形小而 且货源广泛。本指南讨论用 SPI Flash 存储器件配置 Spartan-3E FPGA 所需的连接，并且介绍 SPI 模式的配置流程。本指南还提供一种实用工具，用于在原型开发过程中对选定的 STMicroelectronics 和 Atmel SPI 器件进
ASIC_Design_Flow_Tutorial_with_synopsys
- Tutorial from VCS to IC Compiler for ASIC design using synopsys tool. .