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armok01120249
- arm 开发套件v1.2注册文件,开发嵌入式的必备软件-arm develop suit v1.2 cracker
ESLA601-User-Manual-v-1.2
- ESLA601 逻辑分析仪手册 1.2 版本 中文.-ESLA601 user manual,chinese v1.2.
VerilogHDL-Code-Formatter-V1.2
- 这是一款Verilog代码格式化工具. 用于代码格式美化。您可以根据自己的VerilogHDL格式需求,在右侧控制面板中进行控制,左侧即时显示出当前设置的格式。是一款好用的VerilogHDL代码格式工具。-Format landscaping. According to their own VerilogHDL format requirements, you can in the right side of the control panel to control the real-time
A7105-Datasheet-v1.1
- 无线A7105说明书 0.0 Initial issue. 0.1 Modified specification and add section for TX power setting 0.2 Add top marking info., reflow profile, Carry tape & reel dimensi 0.3 Modify descr iption of state machine and FIFO mode Rename IRQS1/
THDB_D5M_CD
- Terasic TRDB-D5M CD V1.2.0
Quadrature_MACx42_AvalonSt_Input v1.0
- This module does Complex MAC based on Altera Stratix 2 DSP Blocks.
