搜索资源列表
systemverilog
- systemverilog是新出现的一种高级硬件描述和验证语言，这里给出了一些书和文章还有使用vmm方法开发testbench的例子
vmm_exam
- vmm 验证方法学的学习实例（源代码），分步骤剖析整个验证设计过程-vmm verification methodology of learning examples (source code), the design process step by step analysis of the entire verification
scen_gen_in_vmm.tar
- VMM中如果产生激励，特别是复杂的激励，以及如何在testcase中使用和修改这些激励-how to generate stimulus data in VMM
vmm_test
- 怎样在vmm中建立不同的testcase，以测试不同的功能模块-how to build testcase
new_fifo
- 最新的testbench of FIFO ，使用Vmm，VCS，可以大致了解一下VMM的体系-the new fifo VMM testbench
VMM_Hardware_Abstraction_Layer_User_Guide
- synopsys VMM Hardware Abstraction Layer User Guide
VMM_example
- This is a VMM example System Verilog written for a router DUT-This is a VMM example System Verilog written for a router DUT
telecom
- atm通信协议验证平台，采用vmm采用vmm采用v-atm communication protocol validation platform, vmm
memsys_cntrlr
- 存储模型，vmm验证平台，经典-Storage model, vmm verification platform, the classic
vmm_log
- vmm log 验证平台，采用vmm搭建-vmm log verification platform, built by vmm
vmm_rtl_config
- 采用vmm rtl config的例子-Examples of using vmm rtl config
Low-Power-Methodology-Manual-For-System-On-Chip-D
- VMM for Low Power\implement_multi-Volt Methodology
using-the-vmm-scenario-generator
- 介绍基于VMM验证架构的场景激励生成器的使用方法-using the vmm scenario generator
vmm_golden_reference_guide_jan_2010
- 搭建基于vmm架构验证环境的黄金指导手册.-vmm golden reference guide
i2c_master_slave_core_latest.tar
- This design is Wishbone compatible I2C core. This core can work as I2C master as well as slave. VMM Test-bench is also available.
eth_frame_gen
- 帧激励产生器，用于VMM仿真中生成所需要帧以供测试所用-the use for test
VMMing_Testbench_by_Example
- 基于VMM的验证实例，描述了对一个fifo的验证平台-a systemverilog testbench for vmm