维特比译码，卷积编码，verilog编写，2,1,2编码-Victor than decoding, convolution code, verilog write, 2,1,2 coding

用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V