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leijiaqi
- 累加器，一个加法器和一个寄存器构成的累加器，其用途是用于DDS技术的相位累加器 -ACC
zhenxianfashengqi
- 调用SIN输出四路相位不同正弦波发生器，输出信号幅值是0~A-Four different phases called SIN output sine wave generator, the output signal amplitude is 0 ~ ACC
CPU-with-VHDL-16-32
- 在quartus中运行的32位指令集的16位CPU程序，模块化设计，包括MBR, BR, MR, ACC, MAR, PC, IR, CU, ROM, RAM, ALU等模块-In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU
acc
- 全加器，比较器等verilog hdl代码 以及测试代码-Full adder verilog hdl code of the comparator
cpu
- 本代码主要通过VHDL语言描述了一个CPU，包含了MAR,MBR,PC,BR,ALU,ACC等一系列寄存器。-The code is mainly described by VHDL language a CPU contains a series of MAR, MBR, PC, BR, ALU, ACC register.
acc
- This code has function to accumulate
4bit-microprocessor
- This file is 4bit microprocessor that included a variety of modules like ALU,Progrem Counter and ACC etc It is to calculate 4bit binary Topblock is top level module.
code
- 基本元器件代码包括iv nd2 alu acc fa lfsr mux21 等-The basic components of the code include iv nd2 alu acc fa lfsr mux21 etc.