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16位乘法器
- 自已写的一个16X16的乘法器，速度比较慢。初学者练习练习！-own writing an audio Multiplier, speed is relatively slow. Beginners practice practice!
RLC Test
- RLC Test程序,一个电子竞赛的题目。里面有详尽的源代码。-RLC Test procedures, an electronic race issue. There are detailed source code.
一个8位CISC结构的精简CPU
- 一个8位CISC结构的精简CPU，2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler
CPLD的跑馬燈
- cpld的入门交流：CPLD的跑馬燈一个简易型cpld试验电路用VHDL语言遍的-cpld entry exchange : CPLD 5,250 cpld an easy-to-use test circuit using VHDL times the
Verilog DHL数字钟
- 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
avalon_slave_pwm
- NIOS环境PWM的USER LOGIC实例1-NIOS environment PWM USER an example LOGIC
hello_2pwm
- NIOS环境PWM的USER LOGIC实例1-NIOS environment PWM USER an example LOGIC
一个8位处理器结构，源码分析
- 关于一个8位处理器的分析，和源代码，VHDL语言设计，经过测试-on an eight processors, and source code, VHDL design, the test
an-103005-vgagen
- an-103005-vgagen.zip是一个VGA显示控制器，是verilog HDL 编制的
cnt8bc
- 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered. The counter is with an asynch
Avt3S400A_Eval_MB_AN1013_v10_1_03
- This reference design outlines the steps to create a design compatible with a small embedded RTOS, in this case, μC/OS-II from Micrium. This document assumes you have already downloaded Application Note 1013 (AN-1013)
An-Accurate-branch-prediction
- 一种精确的分支预测微处理器模型 关键词 分支预测； 指令级并行； 乱序执行； 分支误预测； 指令预取； 指令窗口大小-An Accurate branch prediction microprocessor model
add-an-IP-to-EDK-hardware-design
- EXCD-1 可编程片上系统 实验例程中的EDK部分 功能：添加一个IP 到硬件设计-EXCD-1 programmable system on chip experimental part of the routine to add an IP to EDK hardware design
An-Introduction-to-FPGA-Design
- An introduction to FPGA design
dividing-an-odd-number-
- Verilog语言实现奇数分频1比1；简单易实现。-Verilog realize dividing an odd number 1-1 Simple easy to realize.
AN-FPGA-IMPLEMENTATION-OF-RIJNDAEL
- AN FPGA IMPLEMENTATION OF RIJNDAEL
an-8-bit-left-shift-register
- 使用VHDL语言设计一个8 位左移移位寄存器。并给出了仿真波形。-Using VHDL to design an 8-bit left shift register. And simulation waveforms.
using-the-gate-light-up-an-LED-lamp
- using the gate light up an LED lamp-Experiment 1 a: using the gate light up an LED lamp
6.An-FPGA-Based-High-Speed-IEEE-754-Double-Precis
- An FPGA Based High Speed IEEE-754 Double Precision Floating Point Multiplier
an i2c master controller
- an i2c master controller written in vhdl