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async--RS232
- async--RS232VERILOG HDL原代码-async -- RS232VERILOG HDL source
UART
- Universal async Transmitter Receiver
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
asyn_counter
- async counter,, test bench included-async counter,, test bench included..
Async-fifo
- Asynchronous Fifo tested and aproved.
GrayCounter2
- gray counter for async FIFO design
async-FIFO
- 采用VHDL实现异步的FIFO程序，是学习FPGA的重点内容-VHDL implementation using asynchronous FIFO procedures, the key elements to learn FPGA! !
ff_nika
- this is simple flipflop async design in vhdl
aFifo.vhd.txt
- Async. FIFO for rtl coding and simulation
async_reset_dff
- 异步复位的D触发器 vhdl fpga xilinx spartan-3e-D flip flop async-reset vhdl fpga xilinx spartan-3e
LFSR_FIFO_GasP
- • LFSR uses global clock > Every stage contains valid data > Data moves in lock-step > Bit sequencing and synchronization implicitly enforced • Async implementation requires explicit control > Not every stage contains
async-fifo
- Verilog codes for asynchrounous fifo design
Async-FIFO-VHDL
- 异步FIFO VHDL代码实现，包括：async_fifo_show_ahead.vhd， async_fifo_show_ahead_rd_task_logic.vhd，async_fifo_show_ahead_wr_task_logic.vhd， sync_r2w.vhd，sync_ram_std_dc.vhd，sync_w2r.vhd-The asynchronous FIFO VHDL code implementation, including: async_fi
async.v
- verilog code for UART module
RX_ASYNC_for_module_UART
- Rx Async for module UART written in Verilog Libero Designer core generator.-Rx Async for module UART written in Verilog Libero Designer core generator.
TX_ASYNC_for_module_UART
- Tx Async fpr module UART written in Verilog Libero core generator.-Tx Async fpr module UART written in Verilog Libero core generator.
async_to_sync_reset
- async reset to sync reset