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BULKFPGA
- 用quartus2编写的,Verilog HDL,测试BULK和FPGA通讯的程序-With quartus2 written, Verilog HDL, testing, and FPGA communication procedures BULK
VHDLvom22.08.2008
- Very simple program for FPGA to write bulk data on CY7C68013A USB controller.
usb1_funct_latest.tar
- USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external mi
68013A_BULK_TRANS
- CY68013A异步BULK传输范例，严格按照时序描述来进行读写，对fifo实现读写，功能完善。-CY68013A asynchronous BULK transmission model, in strict accordance with the temporal descr iption to read and write, read and write to the FIFO implementation, perfect function.
Pre-Emphasis
- A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pree