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CLKCP01
- 液晶显示器320*240脉冲实现，每出现12个clk出一个字节脉冲，每出现40个字节脉冲出一个行脉冲。240行结束出一个帧脉冲.-LCD 320 * 240 pulse realized there every 12 clk byte out a pulse, with each 40-byte burst out a pulse line. 240 firms from the end of a frame pulse.
jop_core_bcfetch
- JOP内核字节码获取，很难找的东东，呕血之作-JOP core byte code access, it is difficult to find the price. Zhi for hematemesis
jop_core_decode
- JOP字节码获取的源码，很重要，具体FPGA中实现-JOP byte code access to the source code is important to achieve specific FPGA
vhdl2009
- 并口通讯代码 并口通讯代码（调试通过） --该代码目前能实现单个字节的收发-Parallel communications code (debugging through) -- The code can now achieve a single byte of Transceivers
VERILOGCOMP
- 设计一个字节（8 位）比较器。 要求：比较两个字节的大小，如a[7:0]大于 b[7:0]输出高电平,否则输出低电平,改写测试 模型,使其能进行比较全面的测试 。 -design a byte (8) for comparison. Requirements : To compare the size of two bytes, as a greater than [7:0] b [7:0] output margin. Otherwise, low-level output, re
SDR_4Mx16_HY57V641620HG_verilogl
- Hynix公司8M byte sdr sdram的verilog语言仿真实现。
crc16_ccitt
- crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module.
I2C.rar
- FPGA实现模拟I2C协议的过程，包括三个模块，i2c_master_bit_ctrl.v完成位传输功能、i2c_master_byte_ctrl.v完成字节传输功能，i2c_master_top.v完成整个程序的控制功能，并提供给外部程序的接口。 ,I2C Analog FPGA implementation of the Protocol process, including the three modules, i2c_master_bit_ctrl.v achieve bit tran
HY57V641620HG.vp.rar
- Hynix公司8M Byte SDR SDRAM的Verilog语言仿真实现,Hynix' s 8M Byte SDR SDRAM Simulation of the Verilog language
trunk-hdlc.rar
- 高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
SDH
- SDH开销的接收处理，要求： 1， A1和A2字节为帧头指示字节，A1为“11110110”，A2为“00101000”，连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机，从连续传输的SDH字节流中找出帧头。 2， E2字节为勤务话通道开销，用于公务联络语音通道，其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。（输出端口包括串行数据和64K串行时钟）
sdh1
- 本段代码是关于SDH帧的操作的一段VHDL的代码。 主要需求为两部分： 1. 从连续传输的SDH字节流中找出帧头。 2. 从SDH字节流中，提取F1字节，并按照要求输出。-This section of code is on the operation of a SDH frame VHDL code. Two main needs: 1. From the continuous transmission of SDH byte stream to find the frame he
send_test
- 输入时钟，可以得到周期性的有效信号以及同步信号，同时可以随时钟输出8个字节的数据-Input clock, can be an effective signal, as well as periodic synchronization signal, at the same time can be 8-byte clock output data
FPGAPROGRAMCHAPTER6
- FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节，然后把它接收回来。 -FPGA development board to write the Verilog code: function is from the client computer sends a byte, and then receive it back.
48_4.12
- 网络通信中的MII接口 通常将4位nibble数据送出，此程序将4位数据组合成8位数据并行输出（8比特==1个字节）。。完全可用 同时包含84转换-The MII network interface usually sent four nibble data, this procedure will be 4-bit data into 8-bit parallel output data (8 bits == 1 byte). . Completely available at the
Flashcontrollerxilinx
- Single power supply operation — Full voltage range: 2.7 to 3.6 volt read, erase, and program operations — Separate VCCQ for 5 volt I/O tolerance n Automated Program and Erase — Page program: 512 + 16 bytes — Block erase: 8 K + 256 bytes
ram32b
- VHDL code for 32 byte RAM
Desktop
- VHDL code for 16 byte ROM & n bit comparator & a full adder
prog-1-store-byte
- 8051 souce code to store byte in the memory.-8051 souce code to to store byte in the memory.
Double-byte-adder-BCD-code
- 将以片内RAM 30H 为起始地址的双字节BCD码 30H和40H为起始地址的双字节BCD码相加，结果放在50H和51H中，程序结束-Will be in RAM30H for the starting address of the double byte BCD code 30H and 40H for the starting address of the double byte BCD code phase, results in 50H and 51H, end of program.