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FPGA_bit_clock_data_recovery
- 基于FPGA的新型数据位同步时钟提取(CDR)实现方法
基于FPGA的软件CDR
- 用FPGA实现CDR，可用于LVDS串化解串，ALTERA原厂工程，实用！
auk_sdsdi
- 用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能-for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
Package
- Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 11
VHDL
- 带有CDR和曼彻斯特编解码的串行接口，代码编译仿真成功过-Control Link Serial Interface with Manchester and CDR
xufeng_cdr
- 软件CDR 设计，在LATTICE 平台上验证通过，含说明PPT。Lattice soft cdr-Lattice soft cdr
SERDES_Introduction
- SERDES & CDR Fundamental SERDES Measurements How to Evaluate a SERDES Device? High Speed Design Consideration
cdr
- 数据时钟恢复，采样8倍率高频时钟进行数据时钟恢复。已通过Modelsim仿真-Data and clock recovery, sampling 8 times the rate of high frequency clock for clock and data recovery. Have been through the Modelsim simulation