搜索资源列表
35_486_bus
- 请注意： 本例的源描述包含文件类型，在学习版上不能编译及模拟， 如果您需要对此描述进行编译及模拟，请与北京理工大学 ASIC研究所联系。 另外，此例与第75例是同一个电路的不同部分的描述，可以 一起参考这两个例子的描述。-Please note : The cases include the descr iption of the source file type, version of the study can not be compiled and simulation, if
dianzizhong
- 这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!-This is my learning process in the middle of the 10-minute program, containing various clock module and the counter, accumulator, and can download, compile!
SECLOCK
- 我从一本书上抄来的 但用MAX+PLUSII编译有些问题 初学者 见谅-from a book copied but with the MAX PLUSII compile some of the problems beginners forgiven
wodevhdl
- vhdl练习实例。在maxplus2中编写，编译通过，正确。-VHDL practice examples. In maxplus2 prepare, compile and correct.
keybyise
- 一个在xilinx公司ise编译环境下仿真成功的键盘操作程序。-a company embarks on the environment and ideally compile successful simulation keyboard operations.
xljc
- VHDL的序列检测源代码，ATERA平台下编译通过。附详细说明及仿真源代码。-Sequence Detection VHDL source code, ATERA platform compile. Report detailed descr iption and simulation of the source code.
led_decode
- 用veilog HDL编的七段译码显示电路。自己做的第一个此类程序，编译仿真通过，感觉不错-veilog HDL series with paragraph 107 of the decoder show circuit. I have done the first such procedure, compile through simulation, feeling good
ISE8.1_loopback
- 硬件平台为Xilinx Spartan3e，编译软件为ISE8.1，实现了九针com口通信，键盘输入回显，switch控制LED功能。-hardware platform for Xilinx Spartan3e, compile software ISE8.1. achieved nine needles com port communication, a return to the keyboard input, LED control switch function.
miaobiao_watch
- 此为秒表程序，具有秒表的一般基本功能，已在MAX+plusII 10.2下编译通过。-stopwatch for this procedure is the general basic stopwatch functions, MAX has been under plusII 10.2 compile.
DDS_sin
- 用VHDL语言实现DDS直接数字频率合成器的设计，采用正弦RAM表，可实现频率可控的正弦数字信号，编译、仿真通过。-VHDL DDS Direct Digital Frequency Synthesizer Design using sinusoidal RAM table achieve controllable frequency sinusoidal digital signal, compile, through simulation.
shzdyb
- 这是在FPGA上实现的数字电压表，用VHDL编写的，已通过编译，仿真验证。-This is the FPGA to achieve the digital voltage meter, prepared by using VHDL, compile and simulation.
stopwatch.rar
- 秒表可计时，用VHDL编译的源代码，从0.1到60秒计时，解压后直接用Quartus打开project即可,Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project
DES.zip
- DES 加密算法的实现，使用硬件描述语言VHDL编写,DES encryption algorithm realization, uses hardware descr iption language VHDL to compile
add4
- 一个四位加法器的VHDL语言实现，并通过编译测试-A four-adder realization of the VHDL language, and compile test
DE2_SD_Card_Audio
- 基于SD卡音乐播发器设计代码,SOPC技术,功能齐全的,编译成功的代码-Based on the SD card music broadcast design code, SOPC technology, full-featured, compile the code successfully
CPU
- quartus7.2下以VHDL编程，分为多个模块，在链接原理图中编译。-quartus7.2 next to VHDL programming is divided into multiple modules, compile the schematic in the link.
divider
- verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
ARM_register
- ARM寄存器组设计的源代码，使用Verilog编程实现，可以编译仿真通过。-将中文译成英语 ARM register set design source code, the use of Verilog programming, you can compile the simulation pass.
liushun
- 流水灯和跑马灯的程序 已经编译 可以用 是quartus的开发环境-Marquee lights and running water has been the procedure can be used to compile the development environment is quartus
DE2_VGA3
- The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow