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quaddecoder_verilog_ise11.2_used_09042010
- Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descr ipted in the Constrained file quad.ucf. To use them, y
Writing-Testbenches-using-System-Verilog.tar
- Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from
time
- 几篇解读FPGA内部时序问题的好文章，从最近本的Tco,Tsu，Th等入门。一直到如何对时序进行约束，如何处理各种影响FPGA时钟的因素。如何读懂时序图（Interpreting the Timing Diagram） -FPGA internal timing problems read several good articles, from the most recent of Tco, Tsu, Th and other entry. How the timing has to be co
UVM_TEST
- UVM 的 入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，还有搭建过程说明。很适合用来学习UVM入门。-This paper describes an approach to using Accellera s UVM, the Universal Verification Methodology, for functional verification by mainstream users. The goal is
ECC in VHDL implementation
- ECC Cryptography is a very Good Cryptography Compared to other public key cryptography, it is helpful for both computationally intensive and resource constrained devices for information security purpose. hope you will enjoy
tnn7_code_201212141110
- 人脸检测与跟踪是一个重要而活跃的研究领域，它在视频监控、生物特征识别、视频编码等领域有着广泛的应用前景。该项目的目标是在FPGA板上实现实时系统来检测和跟踪人脸。人脸检测算法包括肤色分割和图像滤波。通过计算被检测区域的质心来确定人脸的位置。该算法的软件版本独立实现，并在matlab的静止图像上进行测试。虽然从MATLAB到Verilog的转换没有预期的那样顺利，实验结果证明了实时系统的准确性和有效性，甚至在不同的光线、面部姿态和肤色的条件下也是如此。所有硬件实现的计算都是以最小的计算量实时完成的