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  1. aes_verilog

    1下载:
  2. A RTL verilog coding for the project AES, which is a cryptography based concepts
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-23
    • 文件大小:7396016
    • 提供者:siva
  1. BasicDES

    0下载:
  2. The BasicDES Cryptography Core is a small, fast implementation of the DES-56 encryption standard.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:26671
    • 提供者:FPGACore
  1. Handbook_elliptic_curve_cryptography

    0下载:
  2. A wnice to guide to stat Elliptic Curve Cryptography
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-19
    • 文件大小:5222179
    • 提供者:kalidas
  1. -Elliptic

    0下载:
  2. We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coproc
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:117173
    • 提供者:陳曉慧
  1. SIMULATION-AND-SYNTHESIS-OF-TRIPLE-DES-BLOCK-CIPH

    0下载:
  2. This project presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-10
    • 文件大小:5363593
    • 提供者:abilash
  1. ECC in VHDL

    0下载:
  2. The Elliptic Curve Cryptography is One of the best Cryptography schema when implemented on Hardware, This source code shows the best working procedure of this cryptography
  3. 所属分类:VHDL编程

  1. ECC in VHDL implementation

    0下载:
  2. Very Helpful algorithm to implement Elliptic Curve Cryptography in Hardware definition language
  3. 所属分类:VHDL编程

  1. ECC in VHDL

    0下载:
  2. ECC Cryptography in VHDL . Very Helpful for showing
  3. 所属分类:VHDL编程

  1. ECC in VHDL implementation

    0下载:
  2. ECC Cryptography is a very Good Cryptography Compared to other public key cryptography, it is helpful for both computationally intensive and resource constrained devices for information security purpose. hope you will enjoy
  3. 所属分类:VHDL编程

  1. ren_gen

    0下载:
  2. xilinx vhdl code for random number generator and prime number check. it can be used for cryptography
  3. 所属分类:VHDL-FPGA-Verilog

  1. 1

    0下载:
  2. DNA Cryptography and Trellis Algorithm
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-25
    • 文件大小:351232
    • 提供者:THINKFOTECH
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