搜索资源列表
DDR3
- DDR3控制器，基于Altera平台，修改管教后直接可以下载进PFGA-DDR3 controller, based on Altera platform, modify the discipline can be downloaded directly into the PFGA
software
- ddr3 Test program for Altera FPGA Starter Kit
94117c05d50c
- Its a clock Sequence for DDR3 Controller.Hope u find it useful
ddr3_controller1
- ddr3 controller for axi interface
1G-NANDP1G-DDR3-(Rev_01)
- 1G Bit (129Mx8) Nand flash / 1G Bit (8Mx16x8Banks) DDR3 SDRAM
DDR3-SDRAM-Controller
- DDR3的控制器（并带有Testbench），可烧录到FPGA中对内存进行读写，相关技术人员可在该代码上修改用于其他场合-DDR3 controller (with an Testbench), the FPGA can be burned to the memory read and write, the relevant technical staff can modify the code to be used on other occasions
ddr3
- VHDL code sample.this files is the VHDL code for using of DDR3 and DDR2 SDRAM.
Lattice-DDR3
- littice ddr3的仿真教程，主要讲解怎么仿真littce 的ddr3，和littice ddr3的基本知识的讲解-explain the basics of lattice ddr3 simulation tutorial, mainly on how simulation little of ddr3, and littice ddr3 of
DDR3-SDRAM-Verilog-Model
- 官方网站的verilog语言描写的ddr3 sdram仿真模型。各种型号可选。
DDR3 SDRAM Verilog Model
- ddr3的逻辑带么参考，有需要的可以看一下。。。。。。。。。(ddr3 ssscoede code code code)
11_ddr3_test
- fpga ddr3 sdram verilog 黑金的板子(fpga ddr3 sdram verilog)
ddr3_rw_ctrl
- verilog基于DDR3 xilinx IP核 的DDR3的读写控制，方便学习(it is based on DDR3 IP core of xilinx)
ddr3control
- 8位突发长度，一次64bit数据读写，MIG核(DDR3 controll implimention)
11_ddr3_test
- Xilinx Spartan-6 DDR3 test code
ddr3_test_top
- DDR3 test code 測試用的代碼 學習用,簡單的使用DDR3(DDR3 test code for learning verilog code study.)
ddr3_128
- DDR3 读写操作，使用spartan6平台验证。(DDR3 read and write operations,the use of spartan6 platform validation.)
DDR3
- spartan6 里使用DDR3IP核，有教程以及源码(spartan6 with ddr3,source and tutorial)
DDR3的工作原理
- DDR3原理，详细的介绍了DDR3内部结构以及工作原理(DDR3 principle, detailed introduction of the internal structure of DDR3 and the principle of work)
Verilog_1Gb_DDR3_G_Die
- ddr3控制器，速率可达1Gbps，语言使用verilog，已经加入tb(ddr3 controller, can be used to ddr3 control,high speed)
XILINX平台DDR3设计教程
- 从零开始的Xilinx DDR3 控制程序编写教程，利用MIS IP核通过自编逻辑实现对DDR3的读写，强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)