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trans4_16
- 看了好多网了，发现有2to4译码，3to8译码，今天我要用4to16译码，写完了就发了上来-saw a lot of net and found 2to4 decoding, 3to8 decoding, today, I must 4to16 decoding, finished on the fat in the ranks
译码器
- 通过对用硬件描述语言VHDL表示的某个专用部件（如中断控制器、差错控制码编码/译码器，此为译码器）的代码分析，构建它的逻辑结构，加深对相关部件设计技术的理解。 试验平台：MaxPlusII -through the use of VHDL hardware descr iption language said a special components (such as interrupt controllers, error control coding / decoding devic
qdq_new
- 采用Verilog HDL设计,在掌宇智能开发板上得到实现 根据抢答器的原理，整个电路可划分为三部分：采样电路、门控电路和译码电路- Uses Verilog the HDL design, obtains the realization basis on the palm space intelligence development board to snatch the answering principle, the entire electric circuit may divi
Convolutional encoding and Viterbi decoding with k
- 卷积码编码和维特比解码 当K为7 时 供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
gongcehngsheji_477-2
- 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
hamming_decoder
- 汉明编码和解码的VHDL程序，直接解压就可以了-Hamming encoding and decoding process of VHDL, can be directly extracted a
5555
- 微波炉定时器集成电路的设计 1、 控制状态机：工作状态状态转换。 2、 数据装入电路：根据控制信号选择定时时间、测试数据或完成信号的装入。 3、 定时器电路：负责完成烹调过程中的时间递减计数和数据译码供给七段数码显示，同时还可以提供烹调完成时间的状态信号供控制状态机产生完成信号。 -microwave timer IC design a control state machine : state of the state conversion work. 2, data l
man_Verilog
- 曼彻斯特编解码，是Verilog语言代码，不多介绍了，用途非常广泛了-Manchester encoding and decoding is the Verilog language code, introduced a few, a very extensive use
tenbench
- 硬件描述语言,verilog HDL,实现了解码器的设计-hardware descr iption language, verilog HDL, the decoding of Design
decoder(vhdl)
- 这是用VHDL编写的译码程序,程序简单易懂-VHDL prepared decoding procedures that are simple to understand
VERILOG-jpeg
- 用Verilog语言在FPGA上实现JPEG图片的解码，附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
MAPdecodingexample
- MAP decoding is a simple method to decode turbo codes
TAXI
- 基于VHDL的出租车计费器，通过VHDL语言来编程实现计费系统的四个功能块：分频模块，控制模块，计量模块和译码显示模块，最后使用MAX+PLUSII软件来对程序进行仿真，以模拟实现出租车的启动，停止以及等待等过程中的计时，计程和计费功能。-Taxi meter based on VHDL, VHDL language programming through the billing system of the four functional blocks: frequency module, co
MP3audio-decoding-operation
- MP3音频编解码运算中IMDCT算法研究及其FPGA实现-MP3 audio decoding operation IMDCT algorithms and FPGA realizing
JPEG-decoding
- 基于FPGA的JPEG解码算法的研究与实现,对开发JPEG编解码算法有参考价值-FPGA-based JPEG decoding algorithm and implementation of JPEG decoding algorithm on the development of a reference value
ldpc-for-fpga-decoding
- ldpc译码算法的matlab实现，码长960，码率1/2,完全模拟fpga硬件实现语言，量化处理。-ldpc decoding using matalb,code length 960,code rate 1/2
the-decoding-algorithm-of-ldpc
- ldpc译码算法介绍及fpga verilog系统方案设计，包括log_bp算法、min_sum算法、scaling_min_sum算法等-introducing the ldpc code decoding algorithm and the related system design，including the log_bp,the min_sum and the scaling_min_sum
FSK-decoding
- 应用 VHDL 对 FSK 实行译码仿真实现,效果理想-FSK decoding
encoding-decoding
- 卷积码编码译码程序以及其modelsim仿真波形文件等-Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file
decoding-circuit-of-the-digital-keys
- 数字按键译码电路VHDL语言描述，按下第一个键表示输入0，按下第二个键表示输入1，以此类推-VHDL language descr iption of the decoding circuit of the digital keys, press the first key input 0, press the second key input 1, and so on