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VHDL2
- 序列信号发生器： 在系统时钟的作用下能够循环产生一组或多组序列信号的时序电路，（循环产生一组序列信号0111010011011010） 序列检测器： 检测一组或多组又二进制码组成的脉冲序列信号，当序列检测器连续收到一组或多组序列信号，如果与预先设置的码11010相同的时候，输出1，否则输出0. -Sequence of signal generator: the role of the system clock cycle to generate one or more si
sourcefile
- 在Altera公司的Cyclone系列FPGA开发板上试验的按键中断程序，希望对那些学习中断开发的初学者有帮助。 pio_key.v是verilog编写的按键中断程序，对应四个按键，按其中任何一个键都可以发送一个中断； keyint.c是Nios中编写的C程序，用于检测按键的中断，如果检测到中断，会检测是哪个按键按下，从而执行相应的程序！ -In Altera' s Cyclone series FPGA development board interrupt key test
pinlvji
- 用vhdl语言写的频率计，可以实现1khz到1Mhz，当低于1Khz时可实现测周期单位为ms，测量精度达到99 ，用数码管动态显示-Vhdl language written with the frequency meter can be achieved 1khz to 1Mhz, when less than 1Khz cycle when unit for detecting ms, 99 accuracy, dynamic display with digital control
slice
- A technique for constructing a processor from modules,each of which processes one bit-field or “slice” of an operand.Bit slice processors usually consist of an ALU of 1,2,4 or 8-bits and control lines including carry or overflow signals usually inter
OFDM_FPGA
- OFDM的FPGA实现 内含卷积编码 交织，频偏检测 完整的OFDM实现代码 -The FPGA contains OFDM convolutional coding to achieve interleaving, OFDM frequency offset detecting the full implementation code
ass1_2_hamming
- Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a
crc-gen[1]
- hamminag code using verilog this code is desinged for detecting
HDL
- 窜行数据检测器，用于检测一列数据中的特殊字符串-Channeling line data detector for detecting a specific string of data in
ROBOT_CONTROL
- code for xilinx spartan fpga to make robot path control by detecting obstruction using ultrasonic sensor
ds18b20_20130712
- 基于XILINX VERTEX-5的ds18b20温度传感器的状态机控制，使用状态机对一线传感器进行控制，用示波器进行观察。-The design is based on the xilinx vertex-5 aimed to realizing the goal of detecting the temperature through ds18b20.
pingp16
- 改进后的pingpong实例，增加球数至16个，用于检测vga输出,并由相应ucf文件-Improved pingpong example, to increase the number of balls 16, for detecting vga output
fsm
- 检测连续3个1的状态机的VHDL代码，输入11111则输出00111，ISE可以编译仿真，运行-Detecting consecutive three one state machine VHDL code, enter 11111 Output 00111, ISE can compile simulation run
cpc1
- 实现序列检测的功能，对特定数字序列成功的检测-Achieve the function of sequence detection for detecting the success of a particular sequence of numbers
sign_det
- 此程序为符号检测的VHDL程序，用于检测输入数据的最高位符号。-This program is a symbol detection VHDL program for detecting the most significant bit of input data symbols.
code
- razor flipflop used in multiplier for error detecting
extension_booth
- A razor based booth multiplier is used for error detecting
mode_det
- 用于检测时钟的有无，通过输出的信号电平进行指示-For detecting the presence or absence of the clock, by the output signal level is indicated
Sequence-Detector
- 利用状态机设计一个序列检测器，用以检测“1101”。用btn[1]和btn[0]作为输入分别代表1和0，输入的当前数字显示在数码管最后一位，每当新输入一个数字，之前输入的数字左移一位，依次显示出最近输入的四位数字，无输入时数码管不显示任何数字。clk时钟需要分频后才可作为检测时钟（建议分频至190Hz），每当检测到序列中有“1101”出现时，led[0]点亮，即数码显示管上显示“1101”时led[0]点亮；当按下btn[2]时恢复初始状态。-The use of a state machine
xulie
- 序列检测，检测出序列11010后亮灯，文件是用verilog编写的-Sequence detection, after detecting a sequence of 11010 lighting, files are written with verilog
my_cpu
- 计算机组成原理实验代码：单周期Cpu设计，附上检测指令， 在ISE 14.4通过检测-Computer Composition Theory Experiment Code: Cpu single-cycle design, attach detection command, by detecting the ISE 14.4