搜索资源列表
VMM_example
- This is a VMM example System Verilog written for a router DUT-This is a VMM example System Verilog written for a router DUT
ds
- AXI protocal..used to check axi dut
UVM_TEST
- UVM 的 入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，还有搭建过程说明。很适合用来学习UVM入门。-This paper describes an approach to using Accellera s UVM, the Universal Verification Methodology, for functional verification by mainstream users. The goal is
a7
- THIS is the file consists of verification environment for SWITCH(DUT)
eetop.cn_UVM
- UVM 的 入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，(UVM entry example, a complete example of running through. These include the DUT code, the Testbench code,)
2F
- testing testbench to device under test (dut)