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数字锁相环设计源程序
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input freque
Booth_Multiplier
- 布斯乘法器的VHDL程序,下載後直接解壓縮複製貼上到你的EDATOOL就可以.-Booth multiplier VHDL procedures downloaded directly extract copy affixed to the EDATOOL you can.
EDATOOL
- EDA的工具介紹(WORD檔)<沒有解壓縮密碼>-introduced EDA tools (Word stalls) lt; No extract passwords gt;
Full_Adder
- 全加器的VHDL_CODE和TEST_BENCH 無須解壓縮密碼-full adder and the VHDL_CODE TEST_BENCH not extract passwords
dpll0227
- DPLL同步提取有一定效果-DPLL simultaneously extract a certain effect 11111111111111111111111
数字锁相环
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency.
sdh1
- 本段代码是关于SDH帧的操作的一段VHDL的代码。 主要需求为两部分： 1. 从连续传输的SDH字节流中找出帧头。 2. 从SDH字节流中，提取F1字节，并按照要求输出。-This section of code is on the operation of a SDH frame VHDL code. Two main needs: 1. From the continuous transmission of SDH byte stream to find the frame he
SDH_module
- SDH帧同步头的检测，并提取其中的语音信息的模块设计-SDH frame sync detection, and extract audio information module design
20083314141688240
- studydz.com89是解压密码。是关于多功能出租车计价器的设计，有许多创新方面。 -is to extract the password studydz.com89. Taximeter on the multi-function design, there are many innovations.
PLL
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上； 顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is
div-8.5
- 文件格式：VHDL语言。是自己根据具体需要编写的，并通过时序仿真完全正确。改程序是可以直接解压，然后通过Quartus II打开，编译和仿真。十分方便，好用！-File Format: VHDL language. According to the specific needs of their own prepared, and timing simulation entirely correct. Procedures can be directly diverted to extract,
bitsyn
- 在ＦＰＧＡ设计中，当接收的数据需要用数据中提取时钟的时候，需要进行同步处理，该文章详细介绍了数据同步处理的过程-In the FPGA design, when the received data need to extract the clock when the data needs to be synchronized, the article introduced in detail the process of data synchronization processing
vhd_SDH
- 实现从连续传输的SDH字节流中找出帧头、提取F1字节，并按照64K速率分别串行输出F1码流及时钟，其中64K时钟要求基本均匀。文件包含报告文档-SDH transmission from a continuous stream of bytes to identify header, extract F1 bytes, respectively, in accordance with 64K-rate serial output bit stream and clock F1, of which
mfccmain
- It s about speech recognition to extract the features.
ARM_Core
- arm vhdl 源代码，解压后多个文件，经过验证-arm vhdl source code, extract multiple files after the
TIMEFACEDETECTIONANDLIPFEATUREEXTRACTIONUSINGFPGA
- Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bay
FPGA_Interface_Equipment
- 跑马灯、串口、矩阵键盘、蜂鸣器、I2C、数码管、拨码开关 vhdl verilog源代码（精华）-Marquees, serial port, matrix keypad, buzzer, I2C, digital control, DIP switch vhdl verilog source code (extract)
shuzixiabianpin
- 数字下变频中cic滤波器，级联三级，主要功能是抽取滤波，及重要参考资料，包括数字下变频论文-Digital down conversion of cic filter, cascade three-level main function is to extract the filter, and important reference materials, including digital down conversion papers
clock
- vhdl 数字钟工程文件夹 解压就可以用 quartus ii工程文件 -vhdl digital clock project folder can be used to extract the project file quartus ii
CVI-EZUSB-6.12
- FPGA开发板上的USB驱动程序，详情见解压目录文件-FPGA development board' s USB driver, extract the directory file details