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This VHDL code pertains to the DCO model
- code.doc C.1 DCO LEVEL 2 This VHDL code pertains to the DCO model descr iption in Section 6.5.5. The entity declaration of the level 2 DCO is between lines 18 and 39. The VHDL generics or elaboration-phase parameter constants are declared between
run_watch
- 提供一个数字秒表的EDA设计实例，内故有VHDL源代码，并有运行仿真图。-To provide a digital stopwatch the EDA design example, it is within the VHDL source code, and run the simulation of Fig.
lift
- 我自己写的六层电梯程序，用的语言是VHDL，还有仿真的图，非常有用，-I wrote it myself six lift procedures, the language used is VHDL, simulation of the Fig also, very useful,
VHDLkejian
- EDA技术从某种意义上说：学习一种通过软件的方法来高效地完成硬件设计的计算机技术__------VHDL文字说明的系统的功能——系统逻辑描述（算法）——图、VHDL语言(用一套计算机能处理的语言来描述设计结果和设计要求)。 -EDA technology from a sense: to learn a software approach to efficiently complete the hardware design of computer technology __------ V
8.22-出租车计价器VHDL程序与仿真
- 出租车计价器VHDL程序与仿真,文件是word文件,里面有源程序，程序说明，以及仿真结果图。-Taximeter procedures and VHDL simulation, the file is a word file inside the source code, program descr iption, and the simulation results in Fig.
JJ213_program
- 卷积码（213）的编译码，VHDL语言编写的整个工程文件，带有仿真结果图。-Convolution code (213) codec, VHDL language of the whole project file with the simulation results shown in Fig.
waveled
- verilog实现流水灯功能：从左到右，然后从右到左，中间到两边，包含验证图代码、文档具体描述-verilog to achieve water lights function: left to right, then right to left, in the middle to both sides, including the verification FIG code, documentation, detailed descr iption
qnr_verilog
- 量化取整QNR内部主要包括一个divider模块及产生数据输出有效和循环结果到最近整数的电路，包含仿真结果图。-Rounding quantization internal QNR includes a divider module and generates data output valid and circulating the results to the nearest integer circuit, including the simulation results shown in
uwghb
- FIG simulation speed, distance, amplitude three-dimensional image, Use of natural gradient algorithm, Suppressed carrier type differential phase modulation.