搜索资源列表
DDS_Power
- FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table thr
NIOSII_tutorial_code
- NIOSII实例代码。包括系统时钟代码，DMA(Memory to Memory)驱动代码，Fine-gained Flash Access驱动代码,Timestamp驱动代码,ISR代码，Simple Flash Access驱动代码，UART代码
epp212p0223_up
- vhdl对dds的原理设计，由衷要得论文价值。不后悔-right dds VHDL design principle, we sincerely value of fine papers. No regrets
VHDL-Cookbook
- VHDL快速查看 入门手册 还有少量精品例子-VHDL Quick View Getting Started manual was also a small number of fine examples
VHDLCookbook
- The purpose of this booklet is to give you a quick introduction to VHDL. This is done by informally describing the facilities provided by the language, and using examples to illustrate them. This booklet does not fully describe every aspect of
DPRM
- a simple ram using vhdl platform provides to create a fine ram mamory .
reedsolomon
- reed solomon encoder synthesis and simulation is done using verilog and working fine
Project_WorkSpace
- The code i have written is for the patent designed by Jay Hartvigsen, Tony Cheng, Eric Hoang and Buddy Broeker "JTAG/DEBUG INTERFACE". This is meant for the purpose of interfacing the controller to debug its core,this code is working fine n very so
VGAbars_1016
- VGA Bar Generator generates VGA timing and outputs bars of fixed colors. Tested on Xilinx Spartan3 SP305 board and works fine.
FPGA_SOPC_starter
- FPGA的学习入门教程，文章写得非常好，具体细腻，帮助你快速掌握FPGA-FPGA Tutorial learning, the article is written very well, specific fine, to help you quickly master the FPGA
miniuart2
- 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a
spi_vip
- This Verification IP from syswip I tested in one of my project its working fine-This is Verification IP from syswip I tested in one of my project its working fine
AX_Clock_Dithering_AN
- Frequency fine tuning and clock dithering using ACTEL FPGA devices.
FineMeasure
- a ranging fine measure function
DSA_HT12E
- ht12e verilog code working fine.
1602_lcd
- 1602的verilog代码 挺好的 值得学习！-The verilog code 1602 fine is worth learning!
paixu
- 给定一个带期限的作业排序问题, n=5, (p1,p2,p3,p4,p5)=(6,3,4,8,5), (t1,t2,t3,t4,t5)=(2,1,2,1,1), (d1,d2,d3,d4,d5)= (3,1,4,2,4), 应用FIFOBB求使总罚款数最小的可行作业集J, 要求:实现对不同作业排序问题实例的求解，问题实例的输入数据存储在case.txt文件中。-Given a scheduling problem with the operation period, n = 5, (p1, p
fp_prj
- 简单的Testbench设计，对FPGA初学者来说很好用-Simple Testbench design, the FPGA is fine for beginners
decimal_divider20110411
- 这是一个经过验证的精极的除法程序，实现的是有小数的除法。欢迎大家下载-This is a proven very fine division process to achieve is to have a decimal division. Welcome to download
pickit
- A pickit 2 clone that works fine for me and for others