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gcd
- 欧几里得算法求最大公约数电路的Verilog实现，消耗功率较低-Euclid algorithm for the realization of the common denominator Verilog circuit, lower power consumption
gcd
- 这是一个求最大公约数的verilog源码-this is a verilog source code which can count the greatest common divider .
GCD
- 最大公约数的计算,各个源描述的编译顺序:gcd.vhd,gcd_stim.vhd-The common denominator of the calculation, the various sources described in the order of the compiler: gcd.vhd, gcd_stim.vhd
VHDLcodes
- Behavioral descr iption of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral descr iption of ALU, RAM MODULE,
VHDLvsVerilog
- This document is in two parts. The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their differences. The second part contains a worked example of a model that computes the Greatest Common Divisor
gcd
- 求最大公约数的vhdl 源代码 gcd-gcd
gcd
- this a program to calculate the gcd of two numbers and then display the result-this is a program to calculate the gcd of two numbers and then display the result
gcd_lcm
- 求两个100以内整数的最大公约数和最小公倍数，只用加法和减法运算-Find the greatest common divisor of two integers less than 100 and the least common multiple, only addition and subtraction
GCD
- Verilog 最大公约数设计RTL级代码和芯片设计图-Verilog GCD Design and synthesis layout
gcd
- 在VHDL里面实现一个简单的GCD算法，包含源代码，并且通过了编译和综合。-Inside the VHDL to implement a simple GCD algorithm, including source code, and through the compilation and synthesis.
gcd3
- 用verilog代码编写的GCD即找两个数之间的最大公约数的FPGA工程。-Verilog code written with the GCD of two numbers that find the common denominator between the FPGA project.
gcd_performence
- 基于流水线设计的性能优先的gcd算法的verilog 代码 频率可达500M-based pipeline design gcd for high clock
gcd
- 分别基于功耗优先和性能优先的欧几里得求最大公约数算法 包括说明文档-based performence and power design for gcd cotain the instruction word
GCD1
- GCD算法的FSMD实现。即利用有限状态机和数据路径-GCD algorithm order which FSMD using finite state machine and data path
gcd2
- GCD算法的FSM+D实现。即利用有限状态机和数据路径分开-GCD algorithm of the FSM + D realize it is using finite state machine and data path separate
PipeLine-GCD-DSP
- 流水线结构的最大公约数处理器，处理的数据为32bit,采用64级流水线实现。-A pipeline sturcture GCD DAC, data width is 32bit.
Verilog-code-for-finding-GCD
- State machine implemented in verilog to find GCD of two 8 bit numbers. Two files are included (module and its testbench)
GCD-CALCULATOR
- GCD CALCULATOR (ESD book figure 2.11) Weijun Zhang, 04/2001 we can put all the components in one document(gcd2.vhd) or put them in separate files this is the example of RT level modeling (FSM + DataPath) the code is synthesize
GCD
- synthesis GCD using systemc
GCD calculator
- gcd calculator is a module that if two parameter has egual value ...