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DecimationFilterDesignforDDCandImplementingItwithF
- 本文介绍了在数字下变频(DDC) 中的抽取滤波器系统设计方法和具体实现方案。采用CIC 滤波器、HB 滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性
FIR_TEST
- 应用matlab 软件设计了下变频器中的CIC、HB、FIR滤波器等核心模块，并将各模块融为一体从软件实现的角度完成了对系统的搭建和功能仿真。-About such key algorithms as CIC, HB, FIR of each module in down- conversion, discussion, abstraction and summarization are given in this paper. Using the MATLAB software, we des
HB_VHDL
- 抽取式HB滤波器基于FPGA的优化实现，里面详细介绍了这个-HB removable filter optimization based on FPGA implementation, which introduces the
cic_hb
- 用FPGA设计的cic和hb滤波器（积分疏状滤波器核半带滤波器）初学FPGA 的同学可以看一下啊-Using the FPGA design cic and hb filter (integral scanty shape filter nuclear half took filter)
CIC-NCO-HB-FIR
- 数字下变频的论文，包含各个模块的设计，其中有CIC,HB,FIR,NCO等模块和源代码。-Digital down conversion papers, including the design of each module, including CIC, HB, FIR, NCO, modules and source code.
DDC_matlab
- 实现数字变下频的matlab程序，CIC,HB,FIR滤波器代码都在其中-Realize digital variable frequency under matlab, CIC, HB, FIR filter code in it
Verilog
- 七段数码管译码器.(Verilog)[FPGA]第一个Verilog程序,七段共阴数码管摸索了好几天,终于能完成敲入代码、综合、仿真、绑定引脚至下载的全套工作了 -. 七段数码管的lookup table module SEG7_LUT ( input [3:0] iDIG, output reg [6:0] oSEG ) always@(iDIG) begin case(iDIG) 4 h1: oSEG = 7 b1111
3-ddc-cic_5hb_firmatlab-testbench)
- 三通道上下变频cic_5hb_firmatlab仿真程序-Three-channel down conversion cic hb fir matlab simulation program