搜索资源列表
verilog SDRAM core
- 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
7SegClock_HLD3
- 基于fpga和xinlinx ise 的7段码led显示程序，希望对你有所帮助-and ideally xinlinx 7 of the code led display program, and I hope to help you
Game_HLD3
- 基于fpga和xinlinx ise的小游戏的vhdl程序，希望对你有所帮助！-xinlinx and they simply based on the small game and ideally the VHDL process, and I hope to help you!
Max232ForHLD3(20040913)(OK)
- 基于fpga和xinlinx ise的串行通信vhdl程序，希望对你有所帮助！-xinlinx and ideally serial communications VHDL process, and I hope to help you!
Mouse_HLD3
- 基于fpga和xinlinx ise的鼠标应用vhdl程序，希望对你有所帮助！-and they simply based on the mouse xinlinx ideally VHDL application procedures, and I hope to help you!
Music_HLD3
- 基于fpga和xinlinx ise的音乐播放器vhdl程序，希望对你有所帮助！-and xinlinx ideally music player VHDL process, and I hope to help you!
PLW
- 电子密码锁的vhdl编程实现，不知以前有没有人做过的。-electronic locks VHDL programming, I wonder if the past is not done.
trans4_16
- 看了好多网了，发现有2to4译码，3to8译码，今天我要用4to16译码，写完了就发了上来-saw a lot of net and found 2to4 decoding, 3to8 decoding, today, I must 4to16 decoding, finished on the fat in the ranks
anjian
- 按键输入模块（key）： --可编程延时发生器（数字同步机）的前端输入模块：0－9十个数字键按键输入模块原型 --前端模块：消抖 --对i0－i9十个输入端的两点要求： --（1）输入端要保证一段时间的稳定高电平 --（2）不能同时按下两个或多于两个的键 --后级模块：1、编码；2、可变模计数器 --编码模块：8线－4线（0－8 BCD码） --可变模计数器模块：以编码模块输出的32位BCD码为模值-button input module (key) : -- p
lightW
- 一個LCD燈的小程序。不是我寫的。我只負責了調試。適用在ACEXEP1K30QC208-3上。我跑了SIMULATOR，管腳連接標示了。我也下在電路板上試過了，沒有問題。要用到實驗板上的兄弟們把CLK1改到TESTOUT3或者0就好了。綫幫助新手，人人有責。-a small LCD lights procedures. I did not write. I am only responsible for the debugging. Apply in ACEXEP1K30QC208-3 on.
伪随机序列的说明和源代码
- 可控m序列产生器我分成四个小模块来做，M，M1，M2，M3分别对应为：m序列产生器、控制器、码长选择器、码速率选择器。-controllable m-sequence generator, I divided into four small modules do, M, M1, M2, M3, respectively : m-sequence generator, controller, code-selector, code rate selector.
VHDL例程
- 有关VHDL的大量例程，对学习VHDL编程的人具有很大的帮助，不可不看-lot of routines, to learn VHDL programming of great help, I can not see
VHDL的编程实例
- 别人的一些常用的VHDL源代码,希望对各位有用!-some others used the VHDL source code, and I hope to you and useful!
数据选择器vhd源代码
- 数据选择器，半加器，3-8译码器vhd源代码。是最近学校的实验内容。我要成会员，所以都发上来供大家参考。-data selection, half-adder ,3-8 decoder vhd source code. Recent experimental schools content. I want to become members and therefore has made onto for reference.
双路脉冲发生器（veralog）
- Verilog HDL 程序 双路脉冲发生器的代码 包含了键盘控制，LED显示，脉冲发生，脉冲频率测量模块 是我自己写得，希望能对你有帮助，有问题可以mail：shaojunwu1@163.com-Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse frequency measurement module is wr
miniMIPS
- 这是一个基于mips-I结构的处理器,32bit,冯诺依曼结构-This is based on a MIPS - I structure of the processor, 32bit, von Neumann structure
bono_evb_cpld_1.2.rar
- sources of CPLD (fpga) from freescale i.MX27 Avanced Designe System Develpment Kit board,sources of CPLD (fpga) from freescale i.MX27 Avanced Designe System Develpment Kit board
oc_i2c_master
- I 2 C 是两线双向的串行接口，非常适合芯片级的通讯。由于 SOPC Builder并未提供 I 2 C 内核， 本节所描述的 I 2 C 内核是 Richard Herveille 制作的并发布到网上去的免费核。 关于 I 2 C 核的使用方法，请见光盘中 oc_i2c_master文件夹下的使用说明.txt。 -I 2 C is a 2-line bidirectional serial interface, very suitable for ch
ofdmbaseband
- the OFDM PHY is adaptive therefore it supports multiple schemes BPSK, QPSK, 16-QAM and 64-QAM for data carriers’ modulation. The constellation diagrams are gray mapped and shows the magnitudes I and Q (In-phase and Quadrature) components of e
I.MX51datasheet.pdf.tar
- facecale i.MX515 datasheet