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FIR_VHDL
- FIR滤波器的VHDL代码,可以修改冲击函数的值-FIR filter VHDL code can modify the impact of the value function
shuzisuoxiang
- 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比，DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields has been extremely wide range of
adder
- 采用加法树流水线乘法构造八位乘法器，并分析设计的性能和结果在时钟节拍上落后的影响因素。 -Multiplication using adder tree structure line 8 multiplier, the design and analysis of the results of the performance and beat the clock on the impact of the factors behind.
FPGA_design_of_the_impact_factor_of_the_clock
- 影响FPGA设计中时钟因素的探讨,能帮组FPGA的设计-FPGA design of the impact factor of the clock，and can help the FPGA design
pwm
- ：随机脉宽调制是解决交流调速系统 中声学噪声的直接有效方法。随机零矢 量分 布是一种很好 的随 机方法，但其不对称的开关函数使其不适用于传统的电流采样方法。通过仿真表明 PWM周期中点采样的方 法无法得到准确的平均值，在分析不对称模式引起的纹波电流对电流平均值影响的基础上，提出了一种适合 于 RZV分布 的电流采样方法 。仿真结果证实该方法简单可行 。 -: Random pulse width modulation speed control system to solve
VerilogCodingStylesForImprovedSimulationEfficiency
- This paper details different coding styles and their impact on Verilog-XL simulation efficiency. -This paper details different coding styles and their impact on Verilog-XL simulation efficiency.This paper details different coding styles and their
XC4VLX60MB_Lab5_PROM_ISE91
- XCVLXMB the board Xilinx SRAM_BASED FPGA design is the main element Pieces, SRAM_BASED the FPGA, the design began to verify the results, may experience many changes, this time as long as the JTAG s DOWNLOAD CABLE with the IMPACT software is conti
DDC_Ver1.0
- 数字下变频（DDC）在如今基于软件无线电的架构中对系统的整体性能决定性的影响，代码为基于Matlab的4通道DDC程序，程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值-Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code
crossnoise-R5
- In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem affecting circuit reliability. Even though FPGAs are more immune
Oscilloscope
- The design is designed partly in VHDL, partly in schematic drawings and targets a Xilinx Spartan-2E FPGA. However, since the design was tailored specifically for the aforementioned boards it is highly unlikely that it can be ported to other hardware.
ThesummaryofSoCOCB
- 随着以IP核复用为基础的SoC设计技术的发展，工业界及研究组织积极从事相关IP互联标准 方案的制定工作，从目前的研究和发展看，影响力较大的有IBM 公司的CoreConnect、ARM 公司的AMBA 和Silicore Corp公司的Wishbone。基于现有IP互联接口标准技术的发展现状，本文对这三种SoC总线技 术进行了详细介绍。-Along with the IP core reuse-based SoC design technology, industry and res
top_PR
- 用户将使用具有局部重配置能力的ISE 12.1，进行综合HDL模块并完成设计。之后，使用PlanAhead12.1来布局规划设计，并内部调用执行和分析工具，包括：调用FPGA Editor查看设计实现 调用Constraint Editor创建时序约束；用Timing Analyzer进行时序分析。最后，用户可以用XUPV5开发板来进行硬件验证，并用iMPACT软件来下载全局和局部比特流。-Top-level design dynamically reconfigurable, static l
DC-motor-controller-and-its-control
- 基于VHDL语言的直流电机控制器及其控制，本控制系统的总体结构,下位机是整个高频疲劳试验机控制器的核心。用于实现产生控制试验机的控制信号和数据，反馈信号的处理，以及和上位机进行数据通信。其控制功能强弱也直接影响着整个控制器性能的好坏-DC Motor Based on VHDL controller and its control, the overall structure of the control system, the next bit machine is the high-freq
chuankoushoufa
- 接收代码: 对接收数据的采样频率：16X9600HZ 接收代码编写思路： 首先判断起始位,没有数据传输时，起始位为“1”的状态，当有数据时起始位为“0”。因为采样的频率是通信频率的16倍，所以当连续8次（数据位正中间）采集为“0”时就认为是有数据到来。那么可以开始采集数据位，以后每隔16个脉冲采集一个数据（每个数据的正中央，不易发生畸变的部分），连续采样8次，即完成数据位的采集。最后实现串并转换。如此重复即可。（因为通信已经预约好，停止位和校验位都为“1”，不会对数据产生影响。）
INOUT
- 一个实现特定功能的FPGA程序，使用VHDL语言编写，用于排除FPGA影响，检测电路中其他芯片是否正常工作-A function of the FPGA to achieve a specific program, the use of VHDL language for FPGA exclude the impact of other chip detection circuit is working properly
fir_lms-adaptive-filter
- 采用VHDL语言编写的fir级联结构的LMS自适应滤波器，方便学习研究自适应滤波器有关参数实际实现的影响-Using VHDL language fir cascade structure of LMS adaptive filter, adaptive filter to facilitate study and research the impact of the actual implementation of the relevant parameters
svc123
- 动态无功补偿装置，仅仅是补偿无功功率，它的响应很快，就是补偿速度很快。 有源滤波器，主要是用来滤除电网中的谐波，但是它有补偿无功功率的能力，而且补偿的响应速度更快。目前的产品中，有源滤波器的功率容量相对较小，而且价格较高，所以鲜有专门用来做无功补偿动态无功补偿装置，仅仅是补偿无功功率，它的响应很快，就是补偿速度很快。 有源滤波器，主要是用来滤除电网中的谐波，但是它有补偿无功功率的能力，而且补偿的响应速度更快。目前的产品中，有源滤波器的功率容量相对较小，而且价格较高，所以鲜有专门用来做
tst_bench_top
- I2C控制总线的测试平台testbench，用于验证I2C主机冲击交互的正确性-I2C control bus test platform testbench, used to verify the correctness of the interaction I2C master impact
VLSI4
- The mismatch drift of dynamic circuits, which must be corrected by precharging before activation, is a fundamental process and device reliability issue for very large scale integration (VLSI) circuits. In this paper, we report the consequences
2
- for the first time, the impact of hotcarrier-induced gate capacitance variation on dynamic circuits in a VLSI chip. To investigate the mismatch drift due to the hot-carrier-induced gate capacitance variation, internal probing was performed at